Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23645
Change subject: mainboard/google/meowth: Enable ECT back ......................................................................
mainboard/google/meowth: Enable ECT back
Previously ECT had been disabled during meowth P0 bring up, on D0 stepping system and FSP version 7.x.20.52, disable ECT will cause MRC training failure and stuck at post code 00D5h.
BUG=b.72473063 TEST=Apply patch and build coreboot image, flash into meowth P0 system with D0 stepping silicon installed, system can pass MRC training and boot up into OS.
Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/mainboard/google/zoombini/variants/meowth/memory.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/23645/1
diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c index 7c2fa20..c72ffea 100644 --- a/src/mainboard/google/zoombini/variants/meowth/memory.c +++ b/src/mainboard/google/zoombini/variants/meowth/memory.c @@ -82,8 +82,8 @@ /* Meowth is a non-interleaved design */ .dq_pins_interleaved = 0,
- /* Disable Early Command Training */ - .ect = 0, + /* Enable Early Command Training */ + .ect = 1, };
const struct lpddr4_cfg *variant_lpddr4_config(void)