Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34896 )
Change subject: mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region ......................................................................
mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to decompress and load more data from CBFS in romstage.
BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot
Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66 Signed-off-by: Tristan Shieh tristan.shieh@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/memlayout.ld 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/34896/1
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index d8d5f66..73c880a 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -32,11 +32,11 @@ VBOOT2_TPM_LOG(0x00103000, 2K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) - TIMESTAMP(0x0010B000, 4K) - STACK(0x0010C000, 16K) - TTB(0x00110000, 28K) - DMA_COHERENT(0x00117000, 4K) + PRERAM_CBFS_CACHE(0x00107004, 48K - 4) + TIMESTAMP(0x00113000, 4K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) SRAM_END(0x00120000)
SRAM_L2C_START(0x00200000)
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34896 )
Change subject: mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34896 )
Change subject: mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region ......................................................................
mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to decompress and load more data from CBFS in romstage.
BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot
Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66 Signed-off-by: Tristan Shieh tristan.shieh@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896 Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8183/include/soc/memlayout.ld 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index d8d5f66..73c880a 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -32,11 +32,11 @@ VBOOT2_TPM_LOG(0x00103000, 2K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) - TIMESTAMP(0x0010B000, 4K) - STACK(0x0010C000, 16K) - TTB(0x00110000, 28K) - DMA_COHERENT(0x00117000, 4K) + PRERAM_CBFS_CACHE(0x00107004, 48K - 4) + TIMESTAMP(0x00113000, 4K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) SRAM_END(0x00120000)
SRAM_L2C_START(0x00200000)
-
Hung-Te Lin (Code Review) -
Patrick Georgi (Code Review)
-
Tristan Hsieh (Code Review)