[M] Change in coreboot[main]: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1

[Jan Samek (Code Review)]

Attention is currently required from: Jan Samek, Johannes Hahn, Werner Zeh.

Hello Johannes Hahn, Mario Scheithauer, Werner Zeh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/80186?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
......................................................................

mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1

As a result of hardware changes on this board, the PHY previously
routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake
SoC.

This patch changes the device PCI ID in the board's devicetree and
accordingly, the GPIO configuration.

BUG=none
TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE
are working, while PSE GbE 1 remains inactive (not listed by 'ip link')
.

Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b
Signed-off-by: Jan Samek 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
2 files changed, 38 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/80186/2