[S] Change in coreboot[master]: mb/google/brask/var/constitution: update gpio settings

[Morris Hsu (Code Review)]

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73508 )

Change subject: mb/google/brask/var/constitution: update gpio settings
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mb/google/brask/var/constitution: update gpio settings

Remove GPP_D11,GPP_D12 in ramstage, follow baseboard brask setting

Change-Id: I953170f006699e3dc9d6111ded8234f66b9162c7
Signed-off-by: Morris Hsu 
---
M src/mainboard/google/brya/variants/constitution/gpio.c
1 file changed, 12 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/73508/1

diff --git a/src/mainboard/google/brya/variants/constitution/gpio.c b/src/mainboard/google/brya/variants/constitution/gpio.c
index 90b363b..6ad88ff 100644
--- a/src/mainboard/google/brya/variants/constitution/gpio.c
+++ b/src/mainboard/google/brya/variants/constitution/gpio.c
@@ -29,10 +29,6 @@
    PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
    /* D10  : ISH_SPI_CS# ==> NC */
    PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
-	/* D11  : ISH_SPI_MISO ==> NC */
-	PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
-	/* D12  : ISH_SPI_MOSI ==> NC */
-	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
    /* D13  : ISH_UART0_RXD ==> PCH_I2C_U3A0_SDA */
    PAD_CFG_NF_LOCK(GPP_D13, NONE, NF3, LOCK_CONFIG),
    /* D14  : ISH_UART0_TXD ==> PCH_I2C_U3A0_SCL */