Change in coreboot[master]: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=None
BRANCH=None
TEST=Verified Fan control functionality for TSR0/1 on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 78 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/1

diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl
index ca128c9..534ab9b 100644
--- a/src/soc/intel/common/acpi/dptf/thermal.asl
+++ b/src/soc/intel/common/acpi/dptf/thermal.asl
@@ -155,6 +155,51 @@
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR0_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+	}
+#endif
+#endif
 }
 #endif

@@ -219,6 +264,39 @@
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+	}
+#endif
+#endif
 }
 #endif

[Sumeet R Pawnikar (Code Review)]

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35127

to look at the new patch set (#2).

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR0/1 on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 78 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/2

[Sumeet R Pawnikar (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35127

to look at the new patch set (#3).

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR0/1 on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 78 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/3

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35127/3/src/soc/intel/common/acpi/d... 
File src/soc/intel/common/acpi/dptf/thermal.asl:

https://review.coreboot.org/c/coreboot/+/35127/3/src/soc/intel/common/acpi/d... 
PS3, Line 299: #endif
Sorry maybe I'm missing something; is there a reason _AC5 and _AC6 were not included here?

[Sumeet R Pawnikar (Code Review)]

Hello Patrick Rudolph, Philip Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35127

to look at the new patch set (#4).

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=None
BRANCH=None
TEST=Verified Fan control functionality for TSR0/1 on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 90 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/4

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35127/3/src/soc/intel/common/acpi/d... 
File src/soc/intel/common/acpi/dptf/thermal.asl:

https://review.coreboot.org/c/coreboot/+/35127/3/src/soc/intel/common/acpi/d... 
PS3, Line 299: #endif
> Sorry maybe I'm missing something; is there a reason _AC5 and _AC6 were not included here?

I missed these. Thanks Tim for finding it.

[Sumeet R Pawnikar (Code Review)]

Hello Patrick Rudolph, Philip Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35127

to look at the new patch set (#5).

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR0/1 on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 90 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/5

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 5: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35127/5/src/soc/intel/common/acpi/d... 
File src/soc/intel/common/acpi/dptf/thermal.asl:

PS5: 
Just curious: Why are these controls added only to TSR0 and TSR1 but not to TSR2 and TSR3?

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 5: -Code-Review

(1 comment)

Good point Fur

https://review.coreboot.org/c/coreboot/+/35127/5/src/soc/intel/common/acpi/d... 
File src/soc/intel/common/acpi/dptf/thermal.asl:

PS5:
> Just curious: Why are these controls added only to TSR0 and TSR1 but not to TSR2 and TSR3?

That's a good point; I think for Hatch we were only using TSR0/1 but if this is in common code, it should be available for 2 and 23 as well.

[Sumeet R Pawnikar (Code Review)]

Hello Patrick Rudolph, Philip Chen, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35127

to look at the new patch set (#6).

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR sensors on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 180 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/6

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 6: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35127/3/src/soc/intel/common/acpi/d... 
File src/soc/intel/common/acpi/dptf/thermal.asl:

https://review.coreboot.org/c/coreboot/+/35127/3/src/soc/intel/common/acpi/d... 
PS3, Line 299: #endif
> I missed these. Thanks Tim for finding it.

Done

https://review.coreboot.org/c/coreboot/+/35127/5/src/soc/intel/common/acpi/d... 
File src/soc/intel/common/acpi/dptf/thermal.asl:

PS5:
> That's a good point; I think for Hatch we were only using TSR0/1 but if this is in common code, it s […]

Done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35127 )

Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
......................................................................

soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR sensors on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35127
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 180 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl
index ca128c9..d41f623 100644
--- a/src/soc/intel/common/acpi/dptf/thermal.asl
+++ b/src/soc/intel/common/acpi/dptf/thermal.asl
@@ -155,6 +155,51 @@
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR0_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+	}
+#endif
+#endif
 }
 #endif

@@ -219,6 +264,51 @@
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6))
+	}
+#endif
+#endif
 }
 #endif

@@ -283,6 +373,51 @@
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR2_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6))
+	}
+#endif
+#endif
 }
 #endif

@@ -347,5 +482,50 @@
    {
    	_SB.PCI0.LPCB.EC0.PATD (TMPI)
    }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR3_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6))
+	}
+#endif
+#endif
 }
 #endif