Sumeet R Pawnikar has uploaded this change for review.

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soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=None
BRANCH=None
TEST=Verified Fan control functionality for TSR0/1 on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
---
M src/soc/intel/common/acpi/dptf/thermal.asl
1 file changed, 78 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/1
diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl
index ca128c9..534ab9b 100644
--- a/src/soc/intel/common/acpi/dptf/thermal.asl
+++ b/src/soc/intel/common/acpi/dptf/thermal.asl
@@ -155,6 +155,51 @@
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR0_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC5
+ Method (_AC5)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC6
+ Method (_AC6)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+ }
+#endif
+#endif
}
#endif

@@ -219,6 +264,39 @@
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+ }
+#endif
+#endif
}
#endif


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Gerrit-Change-Number: 35127
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Gerrit-MessageType: newchange