[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses

[Shuo Liu (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Patrick Rudolph, Ronak Kanabar, Tim Chu, Yu-Ping Wu.

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email )

Change subject: Kconfig: Place XIP components and FIT at high flash addresses
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Patch Set 10:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86570/comment/c2932b70_bad03261?usp... :
PS8, Line 9: CACHE_ROM_SIZE
> Still unclear how CAR has an influence on the cache setup. […]

GNR is not allowed to use more than 16MiB of cache as RAM, which is conceptually a total amount of 16MiB cache footprint to be used. For GNR, the cache as RAM is setup by FSP-T as a single continuous range, as below,

.FsptCoreUpd = {
    	.MicrocodeRegionBase = 0,
    	.MicrocodeRegionLength = 0,
    	.CodeRegionBase = (UINT64)CACHE_ROM_BASE,
    	.CodeRegionLength = (UINT64)CACHE_ROM_SIZE,
    },