Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6596
-gerrit
commit 1141228d9cad1b1144f10f5551ca80414a521a15 Author: Bruce Griffith Bruce.Griffith@se-eng.com Date: Sun Aug 10 17:09:15 2014 -0600
AMD Hudson: Eliminate "extern struct" for access to FCH
The S3 resume and fan control code for Hudson currently bypasses the AGESA API and links directly to AGESA FCH structures. Change the code to access FCH structures through the standard AGESA API if a binary PI is used. The new access for binary PI has not been tested.
There is currently no alternative mechanism available to communicate with the IMC, so fan control is disabled.
Change-Id: Ib0535d90ea0f2b3dadbb9fa7a4f77abc0226b5f5 Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com --- src/southbridge/amd/agesa/hudson/imc.c | 2 ++ src/southbridge/amd/agesa/hudson/resume.c | 31 ++++++++++++++++++++++++------- 2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index d706292..77387f9 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -60,6 +60,7 @@ void imc_reg_init(void) #ifndef __PRE_RAM__ void enable_imc_thermal_zone(void) { +#if !IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) AMD_CONFIG_PARAMS StdHeader; UINT8 FunNum; UINT8 regs[9]; @@ -85,5 +86,6 @@ void enable_imc_thermal_zone(void) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); +#endif } #endif diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 0e986ff..4f38400 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -24,17 +24,32 @@ #include "hudson.h" #include "AGESA.h"
-extern FCH_DATA_BLOCK InitEnvCfgDefault; -extern FCH_INTERFACE FchInterfaceDefault; -extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; -extern FCH_RESET_INTERFACE FchResetInterfaceDefault; - -#define DUMP_FCH_SETTING 0 +#define DUMP_FCH_SETTING \ + (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= 7)
void s3_resume_init_data(void *data) { FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data; - AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader; + +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) + { + AMD_INTERFACE_PARAMS AmdInterfaceParams; + + AmdInterfaceParams.StdHeader = *(FchParams->StdHeader); + AmdInterfaceParams.AgesaFunctionName = FCH_INIT_ENV; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.NewStructPtr = &FchParams; + AmdInterfaceParams.NewStructSize = sizeof (FchParams); + + AmdCreateStruct (&AmdInterfaceParams); + *(FchParams->StdHeader) = AmdInterfaceParams.StdHeader; + } +#else + { + extern FCH_DATA_BLOCK InitEnvCfgDefault; + extern FCH_INTERFACE FchInterfaceDefault; + extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; + extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
*FchParams = InitEnvCfgDefault; FchParams->StdHeader = StdHeader; @@ -110,6 +125,8 @@ void s3_resume_init_data(void *data) FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable; FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; + } +#endif
FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE;