Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44145 )
Change subject: nb/intel/i945: Deduplicate PCIEXBAR decoding ......................................................................
nb/intel/i945: Deduplicate PCIEXBAR decoding
We can use `decode_pcie_bar` instead, if we make it non-static.
Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/northbridge.c 3 files changed, 7 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44145/1
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 75a6da5..232575f 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -3,46 +3,19 @@ #include <types.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <device/pci_ops.h> #include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar;
- dev = pcidev_on_root(0, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current;
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 5275d1b..64a945d 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -364,6 +364,8 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc);
+int decode_pcie_bar(u32 *const base, u32 *const len); + /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 20c9116..103b40f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -12,7 +12,7 @@ #include <cpu/intel/smm_reloc.h> #include "i945.h"
-static int decode_pcie_bar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0;
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44145 )
Change subject: nb/intel/i945: Deduplicate PCIEXBAR decoding ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44145 )
Change subject: nb/intel/i945: Deduplicate PCIEXBAR decoding ......................................................................
nb/intel/i945: Deduplicate PCIEXBAR decoding
We can use `decode_pcie_bar` instead, if we make it non-static.
Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/northbridge.c 3 files changed, 7 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 75a6da5..232575f 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -3,46 +3,19 @@ #include <types.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <device/pci_ops.h> #include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar;
- dev = pcidev_on_root(0, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current;
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 5275d1b..64a945d 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -364,6 +364,8 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc);
+int decode_pcie_bar(u32 *const base, u32 *const len); + /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 20c9116..103b40f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -12,7 +12,7 @@ #include <cpu/intel/smm_reloc.h> #include "i945.h"
-static int decode_pcie_bar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0;
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)