Change in coreboot[master]: mb/intel/cedarisland_crb: Add early gpio table

[Lance Zhao (Code Review)]

Hello Lijian Zhao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40804

to review the following change.

Change subject: mb/intel/cedarisland_crb: Add early gpio table
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mb/intel/cedarisland_crb: Add early gpio table

Several GPIO programm needed before FSP try to enabled ADR by default.

TEST=Build and boot cedarisland platform pass ADR init stage in FSP.

Signed-off-by: Lijian Zhao 
Change-Id: Id17946d899bd77366828ec63852c08bb57918393
---
M src/mainboard/intel/cedarisland_crb/bootblock.c
A src/mainboard/intel/cedarisland_crb/brd_gpio.h
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/40804/1

diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c
index ea82ecc..4f8b30f 100644
--- a/src/mainboard/intel/cedarisland_crb/bootblock.c
+++ b/src/mainboard/intel/cedarisland_crb/bootblock.c
@@ -6,11 +6,14 @@
 #include <device/pci_ops.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <soc/gpio.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <superio/aspeed/ast2400/ast2400.h>
 #include <superio/aspeed/common/aspeed.h>

+#include "brd_gpio.h"
+
 void bootblock_mainboard_early_init(void)
 {
    /* Enable COM1 only */
@@ -22,4 +25,7 @@

const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
    aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+
+	/* Early GPIO Init */
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }
diff --git a/src/mainboard/intel/cedarisland_crb/brd_gpio.h b/src/mainboard/intel/cedarisland_crb/brd_gpio.h
new file mode 100644
index 0000000..8f1967e
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/brd_gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+};

[Lance Zhao (Code Review)]

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40804 )

Change subject: mb/intel/cedarisland_crb: Add early gpio table
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Patch Set 1:
> Patch Set 1:
>
> Hi Lance,
> I think we have already completed work with GPIO for this motherboard in patches:
> https://review.coreboot.org/c/coreboot/+/40734
> https://review.coreboot.org/c/coreboot/+/40736
>
> What do you think of these changes?

thanks, sorry I didn't notice that. Let me abandon my current changes.

[Lance Zhao (Code Review)]

Lance Zhao has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40804 )

Change subject: mb/intel/cedarisland_crb: Add early gpio table
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Abandoned

Already have solution elsewhere