Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller

[Angel Pons (Code Review)]

Attention is currently required from: Wonkyu Kim, Subrata Banik, Kangheui Won, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 )

Change subject: soc/intel/alderlake: Add support for UFS controller
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Patch Set 2: Code-Review+1

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62856/comment/b0846c1b_b6fc1a01 
PS1, Line 8:
> Add an introduction saying what UFS controller does, and where it’s documented?

AIUI, UFS is the successor of eMMC

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/62856/comment/e460fc17_29af6021 
PS2, Line 620: 	/* UFS */
> Can you use is_devfn_enabled function like below?
> s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS);

This would also work, yes.
> s_cfg->UfsEnable[0] is not used?

I think UFS-0 is PCI D18:F5 (0:12.5 in hex) and UFS-1 is PCI D18:F7 (0:12.7 in hex). I have no idea why UFS-0 is unused. I only see balls for one UFS controller in the datasheet.

BTW, looks like document 691222-001 has a typo, it says UFS is PCI D18:F0, but that's actually ISH: https://imgur.com/AiA2TL8.png