[S] Change in coreboot[main]: soc/intel/adl: Handle critical low battery early in romstage

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro.

Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86227?usp=email

to look at the new patch set (#4).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/adl: Handle critical low battery early in romstage
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soc/intel/adl: Handle critical low battery early in romstage

This commit implements early handling of critical low battery
conditions in the romstage for Alder Lake platforms.

A message is displayed to the user via
ux_inform_user_of_poweroff_operation. A short delay is introduced to
allow the user to see the message. A low battery event is logged.
The system is shut down via the Chrome EC.

This early handling prevents the system from proceeding with
boot (while performing firmware update) if the battery is critically
low and ensures a clean shutdown. This is particularly important for
ChromeOS devices.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86227/4