Change in coreboot[master]: cezanne/psp_verstage: add reset/timer svc

[Kangheui Won (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55137

to look at the new patch set (#4).

Change subject: cezanne/psp_verstage: add reset/timer svc
......................................................................

cezanne/psp_verstage: add reset/timer svc

The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.

BUG=b:187906425

Signed-off-by: Kangheui Won 
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
---
M src/soc/amd/cezanne/psp_verstage/chipset.c
M src/soc/amd/cezanne/psp_verstage/svc.c
M src/soc/amd/common/psp_verstage/Makefile.inc
M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
4 files changed, 55 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/55137/4