[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR

[Angel Pons (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu.

Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email )

Change subject: soc/intel/xeon_sp: Reserve PRMRR
......................................................................

Patch Set 7: Code-Review+1

(2 comments)

File src/include/cpu/x86/mtrr.h:

https://review.coreboot.org/c/coreboot/+/84314/comment/a2ca72b3_7b8a2df4?usp... :
PS6, Line 171: /*
             :  * fls64: find least significant bit set in a 64-bit word
             :  * As samples, fls64(0x0) = 64; fls64(0x4400) = 10;
             :  * fls64(0x40400000000) = 34.
             :  */
             : static uint32_t fls64(uint64_t x)
             : {
             : 	uint32_t lo = (uint32_t)x;
             : 	if (lo)
             : 		return fls(lo);
             : 	uint32_t hi = x >> 32;
             : 	return fls(hi) + 32;
             : }
> Acknowledged

CB:85104

File src/soc/intel/xeon_sp/uncore.c:

https://review.coreboot.org/c/coreboot/+/84314/comment/ea88cc0c_446b41b9?usp... :
PS7, Line 173: *base = msr_read(msr_addr);
             : 
             : 	/* Clean the BIT0-BIT11 to get the base address */
             : 	*base = (*base >> RANGE_SHIFT) << RANGE_SHIFT;
I think there's a macro somewhere to do the `(1 << x) - 1` thing but I can't find it:

```suggestion
    /* Mask out bits 0-11 to get the base address */
    *base = msr_read(msr_addr) & ~((1 << RANGE_SHIFT) - 1);
```