Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36646 )
Change subject: ELOG, soc/intel: Avoid some preprocessor use ......................................................................
ELOG, soc/intel: Avoid some preprocessor use
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/baytrail/include/soc/pmc.h M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/smm.c M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/smm.c 7 files changed, 6 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/36646/1
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 09d1322..6cdf419 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,11 +281,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
-#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif
/* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 4f01922..9f10f70 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -38,7 +38,8 @@ uint32_t smi_en;
/* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5063342..744fcf0 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,11 +242,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
-#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif
/* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 364cda5..c108a36 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -39,7 +39,8 @@ uint32_t smi_en;
/* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index af840a2..62201d9 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -262,14 +262,4 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1)
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -#if CONFIG(ELOG) -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - #endif /* _DENVERTON_NS_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 71c8e10..9e588ad 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -285,11 +285,7 @@
uint32_t chipset_prev_sleep_state(uint32_t clear);
-#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 0c40429..fbfd094 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -40,7 +40,8 @@ uint32_t smi_en;
/* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());
Kyösti Mälkki has removed David Guckian from this change. ( https://review.coreboot.org/c/coreboot/+/36646 )
Change subject: ELOG, soc/intel: Avoid some preprocessor use ......................................................................
Removed reviewer David Guckian.
Kyösti Mälkki has removed Vanny E from this change. ( https://review.coreboot.org/c/coreboot/+/36646 )
Change subject: ELOG, soc/intel: Avoid some preprocessor use ......................................................................
Removed reviewer Vanny E.
Kyösti Mälkki has removed Huang Jin from this change. ( https://review.coreboot.org/c/coreboot/+/36646 )
Change subject: ELOG, soc/intel: Avoid some preprocessor use ......................................................................
Removed reviewer Huang Jin.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36646 )
Change subject: ELOG, soc/intel: Avoid some preprocessor use ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36646 )
Change subject: ELOG, soc/intel: Avoid some preprocessor use ......................................................................
ELOG, soc/intel: Avoid some preprocessor use
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/include/soc/pmc.h M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/smm.c M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/smm.c 7 files changed, 6 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 09d1322..6cdf419 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,11 +281,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
-#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif
/* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 4f01922..9f10f70 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -38,7 +38,8 @@ uint32_t smi_en;
/* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5063342..744fcf0 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,11 +242,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
-#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif
/* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 364cda5..c108a36 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -39,7 +39,8 @@ uint32_t smi_en;
/* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index af840a2..62201d9 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -262,14 +262,4 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1)
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -#if CONFIG(ELOG) -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - #endif /* _DENVERTON_NS_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 71c8e10..9e588ad 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -285,11 +285,7 @@
uint32_t chipset_prev_sleep_state(uint32_t clear);
-#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 0c40429..fbfd094 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -40,7 +40,8 @@ uint32_t smi_en;
/* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());
-
Kyösti Mälkki (Code Review) -
Patrick Georgi (Code Review)