Roland Fehér has uploaded this change for review. ( https://review.coreboot.org/29167
Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ......................................................................
util/inteltool: Fix LynxPoint (non-LP) GPIO register map
The GPIO register dumper code for the LynxPoint family PCH chips (Intel 8 Series and C220 Series) was incorreclty using a shortened version of the LynxPoint-LP (Intel 9 Series) GPIO register map. Added the correct register map for the affected chipsets.
Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Signed-off-by: Fehér Roland Ádám feherneoh@gmail.com --- M util/inteltool/gpio.c 1 file changed, 38 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29167/1
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index c38051c..38ce8fa 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -344,6 +344,42 @@
};
+static const io_register_t lynxpoint_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, // GPIO Use Select + { 0x04, 4, "GP_IO_SEL" }, // GPIO Input/Output Select + { 0x08, 4, "RESERVED" }, // Reserved + { 0x0C, 4, "GP_LVL" }, // GPIO Level for Input or Output + { 0x10, 4, "RESERVED" }, // Reserved + { 0x14, 4, "RESERVED" }, // Reserved + { 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable + { 0x1C, 4, "GP_SER_BLINK" }, // GP Serial Blink + { 0x20, 4, "GP_SB_CMDSTS" }, // GP Serial Blink Command Status + { 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data + { 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable + { 0x2A, 2, "GPI_NMI_STS" }, // GPI NMI Status + { 0x2C, 4, "GPI_INV" }, // GPIO Signal Invert + { 0x30, 4, "GPIO_USE_SEL2" }, // GPIO Use Select 2 + { 0x34, 4, "GP_IO_SEL2" }, // GPIO Input/Output Select 2 + { 0x38, 4, "GP_LVL2" }, // GPIO Level for Input or Output 2 + { 0x3C, 4, "RESERVED" }, // Reserved + { 0x40, 4, "GPIO_USE_SEL3" }, // GPIO Use Select 3 + { 0x44, 4, "GP_IO_SEL3" }, // GPIO Input/Output Select 3 + { 0x48, 4, "GP_LVL3" }, // GPIO Level for Input or Output 3 + { 0x4C, 4, "RESERVED" }, // Reserved + { 0x50, 4, "RESERVED" }, // Reserved + { 0x54, 4, "RESERVED" }, // Reserved + { 0x58, 4, "RESERVED" }, // Reserved + { 0x5C, 4, "RESERVED" }, // Reserved + { 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1 + { 0x64, 4, "GP_RST_SEL2" }, // GPIO Reset Select 2 + { 0x68, 4, "GP_RST_SEL3" }, // GPIO Reset Select 3 + { 0x6C, 4, "RESERVED" }, // Reserved + { 0x70, 4, "RESERVED" }, // Reserved + { 0x74, 4, "RESERVED" }, // Reserved + { 0x78, 4, "RESERVED" }, // Reserved + { 0x7C, 4, "RESERVED" }, // Reserved +}; + /* Default values for Cougar Point desktop chipsets */ static const gpio_default_t cp_pch_desktop_defaults[] = { { 0x00, 0xb96ba1ff }, @@ -869,9 +905,8 @@ case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; - gpio_registers = lynxpoint_lp_gpio_registers; - /* Shares register locations but has less of them */ - size = 29; + gpio_registers = lynxpoint_gpio_registers; + size = ARRAY_SIZE(lynxpoint_gpio_registers); break; case PCI_DEVICE_ID_INTEL_3400: case PCI_DEVICE_ID_INTEL_3420: