Change in coreboot[master]: mb/intel/adlrvp_m: Fix to Enable PCIe x1 Slot

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57053 )

Change subject: mb/intel/adlrvp_m: Fix to Enable PCIe x1 Slot
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mb/intel/adlrvp_m: Fix to Enable PCIe x1 Slot

This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0

TEST = show device command:
    $ lspci -s 00:19.0
    expect this:
    00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5

Signed-off-by: Cliff Huang 
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/gpio_m.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index f6230cf..12048dc 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -26,6 +26,8 @@
    PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
    /* D15 : WWAN_DISABLE_N */
    PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	/* D17 : PCIE SLOT1 WAKE N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT),
    /* D18 : WWAN WAKE N*/
    PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
    /* H23 : CLKREQ5_WWAN_N */
@@ -45,6 +47,8 @@
    PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
    /* F6 : GPPC_F6_CNV_PA_BLANKING */
    PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F10 : GPPC_F10 X1_Slot_RESET */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
    /* H8 : CNV_MFUART2_RXD */
    PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
    /* H9 : CNV_MFUART2_TXD */