Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
mb/google: Udpate processor power limits configuration
Update processor power limit configuration parameters for atom based systems.
BRANCH=None BUG=None TEST=None
Change-Id: I0833edb1f4fa81f83cd72c254a0fefd72ef15d20 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb 7 files changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40340/1
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 9253f11..28141bf 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -42,12 +42,12 @@ register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_N_63_32"
- # PL1 override 10000 mW: Due to error in the energy calculation for + # PL1 override 10 W: Due to error in the energy calculation for # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 10W. - register "tdp_pl1_override_mw" = "10000" + register "tdp_pl1_override" = "10" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index cbc2e22..26d9bbf 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -52,12 +52,12 @@ # Enable DPTF register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" + register "tdp_pl1_override" = "12" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 00e63bc..5189b2a 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -52,12 +52,12 @@ # Enable DPTF register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" + register "tdp_pl1_override" = "12" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f62af8a..822dba8 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -52,12 +52,12 @@ # Enable DPTF register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" + register "tdp_pl1_override" = "12" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index b62704a..56f5a23 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -49,12 +49,12 @@ # Enable DPTF register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" + register "tdp_pl1_override" = "12" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 4edf739..eb06cd4 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -52,12 +52,12 @@ # Enable DPTF register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" + register "tdp_pl1_override" = "12" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 361a4a3..543f6b9 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -56,9 +56,9 @@ register "dptf_enable" = "1"
# PL1 override: 7.5W setting gives a run-time 6W actual - register "tdp_pl1_override_mw" = "7500" + register "tdp_pl1_override" = "7" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "tdp_pl2_override" = "15"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1"
Hello Shelley Chen, Wonkyu Kim, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Caveh Jalali, Tim Wawrzynczak, Puthikorn Voravootivat, Todd Broch, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40340
to look at the new patch set (#2).
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
mb/google: Udpate processor power limits configuration
Update processor power limit configuration parameters based on common code base support.
BRANCH=None BUG=None TEST=None
Change-Id: I0833edb1f4fa81f83cd72c254a0fefd72ef15d20 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/glados/variants/caroline/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/glados/variants/chell/overridetree.cb M src/mainboard/google/glados/variants/glados/overridetree.cb M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/duffy/mainboard.c M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/mainboard.c M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/hatch/variants/puff/mainboard.c M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb 49 files changed, 192 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40340/2
Hello Shelley Chen, build bot (Jenkins), Wonkyu Kim, Furquan Shaikh, Patrick Georgi, Caveh Jalali, Tim Wawrzynczak, Puthikorn Voravootivat, Todd Broch, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40340
to look at the new patch set (#3).
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
mb/google: Udpate processor power limits configuration
Update processor power limit configuration parameters based on common code base support.
BRANCH=None BUG=None TEST=None
Change-Id: I0833edb1f4fa81f83cd72c254a0fefd72ef15d20 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/glados/variants/caroline/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/glados/variants/chell/overridetree.cb M src/mainboard/google/glados/variants/glados/overridetree.cb M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/duffy/mainboard.c M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/mainboard.c M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/hatch/variants/puff/mainboard.c M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb 53 files changed, 207 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40340/3
Hello Shelley Chen, build bot (Jenkins), Wonkyu Kim, Furquan Shaikh, Patrick Georgi, Caveh Jalali, Tim Wawrzynczak, Puthikorn Voravootivat, Todd Broch, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40340
to look at the new patch set (#5).
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
mb/google: Udpate processor power limits configuration
Update processor power limit configuration parameters based on common code base support.
BRANCH=None BUG=b:149722146 TEST=None
Change-Id: I0833edb1f4fa81f83cd72c254a0fefd72ef15d20 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/glados/variants/caroline/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/glados/variants/chell/overridetree.cb M src/mainboard/google/glados/variants/glados/overridetree.cb M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/duffy/mainboard.c M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/mainboard.c M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/hatch/variants/puff/mainboard.c M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb 53 files changed, 210 insertions(+), 105 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40340/5
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
Patch Set 5: Code-Review-1
(2 comments)
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG@7 PS5, Line 7: Udpate Update
https://review.coreboot.org/c/coreboot/+/40340/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/mainboard.c:
https://review.coreboot.org/c/coreboot/+/40340/5/src/mainboard/google/poppy/... PS5, Line 34: cfg The cfg pointer hasn't been set yet.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG@7 PS5, Line 7: google Uh, I see more than just google boards...
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG@7 PS5, Line 7: google
Uh, I see more than just google boards...
planning to move these in another patchset if required.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40340/5//COMMIT_MSG@7 PS5, Line 7: google
planning to move these in another patchset if required.
Splitting this into smaller changes would make it easier to review, so it would be much appreciated 😊
In any case, if all boards need to be updated at the same time (so that things build properly), you can use this instead:
mainboard: Update ...
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
Patch Set 5:
Patch Set 5:
(1 comment)
please check the comments of May 05 and 06 on https://review.coreboot.org/c/coreboot/+/39346 for detailed discussion and other dependecy patches on this.
Sumeet R Pawnikar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40340 )
Change subject: mb/google: Udpate processor power limits configuration ......................................................................
Abandoned
submitted another patch for this with more structured manner.
-
Angel Pons (Code Review) -
Nick Vaccaro (Code Review)
-
Sumeet R Pawnikar (Code Review)