Change in coreboot[master]: amd/stoneyridge: Define MTRR S3 structures

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22643

Change subject: amd/stoneyridge: Define MTRR S3 structures
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amd/stoneyridge: Define MTRR S3 structures

In subsequent S3 patches, MTRR settings will be stored in DRAM.  This
is a departure from other examples of AMD support, including the
binaryPI S3 support that was stripped out earlier.

Create structures to simplify saving and restoring the MTRR settings.

Change-Id: Ibd0dbf067e2a752636132de102028b1ebacf2343
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/common/s3_resume.h
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22643/1

diff --git a/src/soc/amd/common/s3_resume.h b/src/soc/amd/common/s3_resume.h
index 39a0712..3e80d72 100644
--- a/src/soc/amd/common/s3_resume.h
+++ b/src/soc/amd/common/s3_resume.h
@@ -16,6 +16,30 @@
 #ifndef __S3_RESUME_H__
 #define __S3_RESUME_H__

+#include <cpu/x86/msr.h>
+
+struct vmtrr_pair {
+	msr_t base;
+	msr_t mask;
+};
+
+#define MAX_VAR_MTRRS 0x20
+struct all_mtrrs {
+	msr_t sys_cfg;
+	msr_t _64k_00;
+	msr_t _16k_80;
+	msr_t _16k_a0;
+	msr_t _4k_c0;
+	msr_t _4k_c8;
+	msr_t _4k_d0;
+	msr_t _4k_d8;
+	msr_t _4k_e0;
+	msr_t _4k_e8;
+	msr_t _4k_f0;
+	msr_t _4k_f8;
+	struct vmtrr_pair vmtrr[MAX_VAR_MTRRS];
+};
+
 void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);

#endif /* __S3_RESUME_H__ */