Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81789?usp=email )
Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO ......................................................................
mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. This CL accounts for those changes.
BUG=b:316421831 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Make sure that brox device still boots up with this change.
Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81789/1
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 337fde1..fba75b2 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -115,7 +115,7 @@ /* b/316421831: GPP_B16/17 need to be enabled when ISH is enabled later on */ /* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> ISH_I2C_EC_SDA (NC) */ PAD_NC(GPP_B16, NONE), - /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> NOTE_BOOK_MODE (NC initially) */ + /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> ISH_I2C_EC_SCL (NC) */ PAD_NC(GPP_B17, NONE), /* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), @@ -198,8 +198,8 @@ PAD_NC(GPP_E7, NONE), /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> SOC_GPP_E9 (NC) */ - PAD_NC(GPP_E9, NONE), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_GPO(GPP_E9, 0, PLTRST), /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */ PAD_CFG_GPI(GPP_E10, NONE, PLTRST), /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> SOC_GPP_E11 (NC) */