Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19256
to look at the new patch set (#6).
Change subject: mb/intel/dg43gt: Add mainboard ......................................................................
mb/intel/dg43gt: Add mainboard
This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash.
What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * PCI * PEG slot with additional patches * Reboot and S3 resume * USB.
What does not work: * GBE (requires descriptor); * Lots of dmesg spam complaining about interrupt storm on HDMI connector.
Not tested: * Booting with descriptor (most likely fixes GBE); * ME with descriptor; * Sound; * All the rest.
Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- A src/mainboard/intel/dg43gt/Kconfig A src/mainboard/intel/dg43gt/Kconfig.name A src/mainboard/intel/dg43gt/Makefile.inc A src/mainboard/intel/dg43gt/acpi/ec.asl A src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi/platform.asl A src/mainboard/intel/dg43gt/acpi/superio.asl A src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl A src/mainboard/intel/dg43gt/acpi_tables.c A src/mainboard/intel/dg43gt/board_info.txt A src/mainboard/intel/dg43gt/cmos.default A src/mainboard/intel/dg43gt/cmos.layout A src/mainboard/intel/dg43gt/cstates.c A src/mainboard/intel/dg43gt/devicetree.cb A src/mainboard/intel/dg43gt/dsdt.asl A src/mainboard/intel/dg43gt/gpio.c A src/mainboard/intel/dg43gt/hda_verb.c A src/mainboard/intel/dg43gt/romstage.c 18 files changed, 901 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19256/6