Patch set updated for coreboot: 2b7546e AGESA: Eliminate compiler warnings in AMD F15 vendorcode
Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3525
-gerrit
commit 2b7546e4f045a039636cc43150206787d47a67c5 Author: Bruce Griffith Bruce.Griffith@se-eng.com Date: Tue Jun 25 14:50:57 2013 -0600
AGESA: Eliminate compiler warnings in AMD F15 vendorcode
This change is mostly type casts to eliminate compile time warnings. These specific changes are mostly cherry-picked from AMD Family 14 code and, as such, contain artifacts copied over from F14. For example, there are a number of UINT64 casts that are commented out rather than removed. This is to maintain consistency between AGESA versions. Ultimately, this is in preparation for turning on warnings as errors for AMD Family 15 server parts.
Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7 Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com --- .../amd/agesa/f15/Include/OptionIdsInstall.h | 12 +++---- .../amd/agesa/f15/Legacy/Proc/Dispatcher.c | 6 ++-- .../amd/agesa/f15/Legacy/Proc/hobTransfer.c | 12 +++---- src/vendorcode/amd/agesa/f15/Porting.h | 2 +- .../Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c | 4 +-- .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c | 4 +-- .../amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c | 4 ++- .../amd/agesa/f15/Proc/CPU/cpuPostInit.c | 2 +- .../amd/agesa/f15/Proc/CPU/heapManager.c | 40 +++++++++++----------- .../amd/agesa/f15/Proc/Common/AmdInitReset.c | 2 +- .../amd/agesa/f15/Proc/Common/S3RestoreState.c | 2 +- .../amd/agesa/f15/Proc/Common/S3SaveState.c | 12 ++++--- .../amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c | 10 +++--- .../amd/agesa/f15/Proc/Mem/Main/mmflow.c | 2 +- 15 files changed, 60 insertions(+), 56 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h index 16cd68c..a2c0034 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h @@ -74,9 +74,9 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE #if (AGESA_ENTRY_INIT_POST == TRUE) #include <mu.h> CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINT32) (UINT64) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINT32) (UINT64) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} + { (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, + { (UINT32) /*(UINT64)*/ MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, + { (UINT32) /*(UINT64)*/ MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} }; #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) #include <mru.h> @@ -94,9 +94,9 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE #endif #else CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"} + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}, + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}, + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"} }; #endif
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c index 7ad4bb9..ae25a49 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c @@ -105,7 +105,7 @@ AmdAgesaDispatcher (
// 2. Try next dispatcher if possible, and we have not already got status back if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher; + ModuleEntry = (MODULE_ENTRY) (mCpuModuleID.NextBlock->ModuleDispatcher); if (ModuleEntry != NULL) { Status = (*ModuleEntry) (ConfigPtr); } @@ -117,10 +117,10 @@ AmdAgesaDispatcher ( ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr; ImageEnd = ImageStart + 4; // Locate/test image base that matches this component - AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, (CHAR8 *) AGESA_ID); + AltImagePtr = LibAmdLocateImage ((VOID *) /* (UINT64) */ImageStart, (VOID *) /* (UINT64) */ImageEnd, 4096, (CHAR8 *) AGESA_ID); if (AltImagePtr != NULL) { //Invoke alternative Image - ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress); + ImageEntry = (IMAGE_ENTRY) (/* (UINT64) */ AltImagePtr + AltImagePtr->EntryPointAddress); Status = (*ImageEntry) (ConfigPtr); } } diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c index f4482ed..b2accb2 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c @@ -209,12 +209,12 @@ CopyHeapToTempRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr; HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
- BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress; + BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress; HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
@@ -308,8 +308,8 @@ CopyHeapToMainRamAtPost ( TotalSize = sizeof (HEAP_MANAGER); SizeOfNodeData = 0; AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr; + BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr; HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
@@ -367,7 +367,7 @@ CopyHeapToMainRamAtPost ( HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; } // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if (StdHeader->HeapBasePtr >= 0x100000) { + if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) { // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); @@ -376,7 +376,7 @@ CopyHeapToMainRamAtPost ( HeapRamVariableMtrr--) { LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && + if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { break; } diff --git a/src/vendorcode/amd/agesa/f15/Porting.h b/src/vendorcode/amd/agesa/f15/Porting.h index 4cd8d1c..776cddc 100644 --- a/src/vendorcode/amd/agesa/f15/Porting.h +++ b/src/vendorcode/amd/agesa/f15/Porting.h @@ -233,7 +233,7 @@ typedef signed char INT8; typedef signed short INT16; typedef signed int INT32; - typedef signed char CHAR8; + typedef char CHAR8; typedef unsigned char UINT8; typedef unsigned short UINT16; typedef unsigned int UINT32; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c index 2f7a061..afcea1d 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c @@ -806,7 +806,7 @@ F15OrEarlySamplesLoadMicrocode (
// Load microcode patch into CPU GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64)(intptr_t) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; // Check if this CPU is OR-B0, expected fix in OR-B1 if ((LogicalId.Revision & AMD_F15_OR_B0) != 0) { diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c index 207d444..c055f5b 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c @@ -216,7 +216,7 @@ SaveDeviceContext ( UINT64 EndAddress; VOID *OrMask;
- StartAddress = (UINT64) DeviceList; + StartAddress = (UINT64)(intptr_t)DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
@@ -280,7 +280,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64) OrMask; + EndAddress = (UINT64)(intptr_t)OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); }
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c index bded7e7..7d1355c 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c @@ -813,7 +813,7 @@ ApUtilSetupIdtForHlt ( DescSize = 8; }
- HandlerOffset = (UINT64) NmiHandler; + HandlerOffset = (UINT64) (UINTN) NmiHandler; NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); @@ -822,7 +822,7 @@ ApUtilSetupIdtForHlt ( NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); NmiIdtDescPtr->Rsvd64 = 0; IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); - IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2); + IdtInfo.Base = (UINT64) (UINTN) NmiIdtDescPtr - (DescSize * 2); IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader); SetIdtr (&IdtInfo , StdHeader); } diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c index 69d198b..d76a372 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c @@ -80,6 +80,7 @@ typedef union { *---------------------------------------------------------------------------------------- */ BOOLEAN +STATIC LoadMicrocode ( IN MICROCODE_PATCH *MicrocodePatchPtr, IN OUT AMD_CONFIG_PARAMS *StdHeader @@ -174,6 +175,7 @@ LoadMicrocodePatch ( * */ BOOLEAN +STATIC LoadMicrocode ( IN MICROCODE_PATCH *MicrocodePatchPtr, IN OUT AMD_CONFIG_PARAMS *StdHeader @@ -183,7 +185,7 @@ LoadMicrocode ( PATCH_LOADER PatchLoaderMsr;
// Load microcode patch into CPU - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64) (UINTN) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c index 901eb80..466e0c4 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c @@ -206,7 +206,7 @@ GetPstateGatherDataAddressAtPost (
AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
- *Ptr = (UINT64 *)(AddressValue); + *Ptr = (UINT64 *)(intptr_t)(AddressValue);
return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c index a02a6a2..f42c35d 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c @@ -156,13 +156,13 @@ HeapManagerInit (
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - HeapBufferPtr = (UINT8 *) StdHeader->HeapBasePtr; + HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
// Check whether the heap manager is already initialized LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) { LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { + if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { // This is not a bug, there are multiple premem basic entry points, // and each will call heap init to make sure create struct will succeed. @@ -178,7 +178,7 @@ HeapManagerInit ( }
// Set variable MTRR base and mask - MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); + MsrData = ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
MsrData |= 0x06; @@ -320,20 +320,20 @@ HeapAllocateBuffer ( AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL;
// Get base address - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress;
// Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64) BaseAddress; + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; }
// Allocate @@ -465,20 +465,20 @@ HeapDeallocateBuffer ( ASSERT (StdHeader != NULL);
HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress;
// Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64) BaseAddress; + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; }
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; @@ -594,20 +594,20 @@ HeapLocateBuffer ( ASSERT (StdHeader != NULL);
HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress;
// Check Heap database is valid if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader); + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); HeapManager = (HEAP_MANAGER *) BaseAddress; if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { // Heap is not available, ASSERT here ASSERT (FALSE); return AGESA_ERROR; } - StdHeader->HeapBasePtr = (UINT64) BaseAddress; + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; } OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); @@ -698,29 +698,29 @@ HeapGetBaseAddress (
// Firstly, we try to see if heap is in cache BaseAddress = HeapGetCurrentBase (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress;
if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { // Secondly, we try to see if heap is in temp memory BaseAddress = UserOptions.CfgHeapDramAddress; - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // Thirdly, we try to see if heap in main memory // by locating with external buffer manager (IBV) AgesaBuffer.StdHeader = *StdHeader; AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { - BaseAddress = (UINT64) AgesaBuffer.BufferPointer; - HeapManager = (HEAP_MANAGER *) BaseAddress; + BaseAddress = (UINT64) (UINTN) AgesaBuffer.BufferPointer; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // No valid heap signature ever found, return a NULL pointer - BaseAddress = 0; + BaseAddress = (UINT64) (UINTN) NULL; } } else { // No heap buffer is allocated by external manager (IBV), return a NULL pointer - BaseAddress = 0; + BaseAddress = (UINT64) (UINTN) NULL; } } } @@ -762,7 +762,7 @@ DeleteFreeSpaceNode ( BUFFER_NODE *PreviousFreeSpaceNode;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress;
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; @@ -821,7 +821,7 @@ InsertFreeSpaceNode ( BUFFER_NODE *PreviousFreeSpaceNode; BUFFER_NODE *InsertedFreeSpaceNode;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress;
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c index 7a2d1a1..7013f67 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c @@ -157,7 +157,7 @@ AmdInitReset (
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
- IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); + IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString);
AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); ASSERT (ResetParams != NULL); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c index 7b9a17d..5f00ec5 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c @@ -166,7 +166,7 @@ S3RestoreStateFromTable ( PCI_ADDR PciAddress; UINTN Index; S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore: Address: 0x%08x\n", (intptr_t)((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { switch (*(UINT16 *) S3SaveTableRecordPtr) { case SAVE_STATE_IO_WRITE_OPCODE: diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c index 4f93379..e4bd926 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c @@ -269,7 +269,7 @@ S3SaveStateSaveWriteOp ( } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); IDS_HDT_CONSOLE (S3_TRACE, "\n"); ); @@ -334,7 +334,7 @@ S3SaveStateSaveReadWriteOp ( } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -410,7 +410,7 @@ S3SaveStateSavePollOp ( } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -482,7 +482,7 @@ S3SaveStateSaveInfoOp ( SaveOffsetPtr->OpCode = OpCode; SaveOffsetPtr->Length = InformationLength; S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", (CHAR8 *)Information); ); LibAmdMemCopy ( (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), @@ -598,6 +598,7 @@ S3SaveDebugOpcodeString ( return (CHAR8*)"DISPATCH"; default: IDS_ERROR_TRAP; + break; } return (CHAR8*)"!!! Unrecognize opcode !!!"; } @@ -640,10 +641,11 @@ S3SaveDebugPrintHexArray ( break; case AccessWidth64: case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); + IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index))[1], ((UINT32*)((UINT64*)Array + Index))[0]); break; default: IDS_ERROR_TRAP; + break; } if (Index < (Count - 1)) { IDS_HDT_CONSOLE (S3_TRACE, ", "); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c index e1218d4..3465825 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c @@ -263,30 +263,30 @@ MemFS3GetDeviceList ( (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
// Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINTN) AllocHeapParams.BufferPtr; for (Die = 0; Die < DieCount; Die ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c index 3129450..f202cf1 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c @@ -378,7 +378,7 @@ MemSPDDataProcess ( AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, (intptr_t)SpdParam.Buffer); } else { DimmSPDPtr->DimmPresent = FALSE; }
-
Bruce Griffith