Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47619 )
Change subject: nb/intel/sandybridge: Clarify register write ......................................................................
nb/intel/sandybridge: Clarify register write
It is necessary to program this register before doing an I/O reset.
Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/47619/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2799103..709217c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1973,6 +1973,7 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
+ /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, .enable_dqs_wl = 5,
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47619 )
Change subject: nb/intel/sandybridge: Clarify register write ......................................................................
Patch Set 5: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47619 )
Change subject: nb/intel/sandybridge: Clarify register write ......................................................................
nb/intel/sandybridge: Clarify register write
It is necessary to program this register before doing an I/O reset.
Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ef4ae45..0939fe6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1954,6 +1954,7 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
+ /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, .enable_dqs_wl = 5,