Change in coreboot[master]: nb/intel/gm45: Allow for PCI BARs above 4G - coreboot-gerrit

6 May 2022


      Attention is currently required from: Arthur Heymans.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64094 )
Change subject: nb/intel/gm45: Allow for PCI BARs above 4G
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Patch Set 1:
(1 comment)
File src/northbridge/intel/gm45/acpi/hostbridge.asl:
https://review.coreboot.org/c/coreboot/+/64094/comment/6aacb5ee_5b46a78b 
PS1, Line 191: 	// PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits
Above `/* */` is used.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b
Gerrit-Change-Number: 64094
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-CC: Paul Menzel paulepanter@mailbox.org
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