Change in ...coreboot[master]: Makefile.inc: Optimize generating the default x86 fmap

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30419

Change subject: Makefile.inc: Optimize generating the default x86 fmap
......................................................................

Makefile.inc: Optimize generating the default x86 fmap

Put the FMAP FMAP region right above the coreboot region.
The other regions like RW_MRC_CACHE and CONSOLE might have alignment
requirements so it makes sense to put those on top. This also
simplifies the generation code a little.

Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans 
---
M Makefile.inc
M util/cbfstool/default-x86.fmd
2 files changed, 12 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30419/1

diff --git a/Makefile.inc b/Makefile.inc
index b25ac6b..85aa19e 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -838,19 +838,16 @@
 FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
 FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f)
 # position and size of flashmap, relative to BIOS_BASE
-FMAP_FMAP_BASE := 0
-FMAP_FMAP_SIZE := 0x200

#
 # X86 CONSOLE FMAP region
 #
 # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
+FMAP_CONSOLE_BASE := 0
 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
 FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
 else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_CONSOLE_BASE := 0
 FMAP_CONSOLE_SIZE := 0
 FMAP_CONSOLE_ENTRY :=
 endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
@@ -860,13 +857,8 @@
 #
 # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
 ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
-ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
+FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add,  $(FMAP_CONSOLE_BASE) \
    $(FMAP_CONSOLE_SIZE)), 0x10000)
-else
-FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \
-	$(FMAP_FMAP_SIZE)), 0x10000)
-endif
 FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
 FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
 else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
@@ -876,14 +868,18 @@
 endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)

#
+# X86 FMAP region
+#
+#
+# position, size
+FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE))
+FMAP_FMAP_SIZE := 0x200
+
+#
 # X86 COREBOOT default cbfs FMAP region
 #
 # position and size of CBFS, relative to BIOS_BASE
-ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
-else
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE))
-endif
+FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 else # ifeq ($(CONFIG_ARCH_X86),y)
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
index 1f1aa43..174db1f 100644
--- a/util/cbfstool/default-x86.fmd
+++ b/util/cbfstool/default-x86.fmd
@@ -9,9 +9,9 @@

FLASH@##ROM_BASE## ##ROM_SIZE## {
    BIOS@##BIOS_BASE## ##BIOS_SIZE## {
-		FMAP@##FMAP_BASE## ##FMAP_SIZE##
    	##CONSOLE_ENTRY##
    	##MRC_CACHE_ENTRY##
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
    	COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
    }
 }

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30419 )

Change subject: Makefile.inc: Optimize generating the default x86 fmap
......................................................................

Patch Set 4: Code-Review+2

(1 comment)

https://review.coreboot.org/#/c/30419/4/util/cbfstool/default-x86.fmd 
File util/cbfstool/default-x86.fmd:

https://review.coreboot.org/#/c/30419/4/util/cbfstool/default-x86.fmd@14 
PS4, Line 14: 		FMAP@##FMAP_BASE## ##FMAP_SIZE##
The only concern I have is that I think some implementations do a binary search for the fmap, which will slow down with this layout. OTOH, I don't think any of these are in the critical path (eg. in coreboot), so...

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30419 )

Change subject: Makefile.inc: Optimize generating the default x86 fmap
......................................................................

Makefile.inc: Optimize generating the default x86 fmap

Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.

Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi 
Tested-by: build bot (Jenkins) 
---
M Makefile.inc
M util/cbfstool/default-x86.fmd
2 files changed, 12 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/Makefile.inc b/Makefile.inc
index 7d6bc7c..3ec1e63 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -852,19 +852,16 @@
 FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
 FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f)
 # position and size of flashmap, relative to BIOS_BASE
-FMAP_FMAP_BASE := 0
-FMAP_FMAP_SIZE := 0x200

#
 # X86 CONSOLE FMAP region
 #
 # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
+FMAP_CONSOLE_BASE := 0
 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
 FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
 else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_CONSOLE_BASE := 0
 FMAP_CONSOLE_SIZE := 0
 FMAP_CONSOLE_ENTRY :=
 endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
@@ -874,13 +871,8 @@
 #
 # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
 ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
-ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
+FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add,  $(FMAP_CONSOLE_BASE) \
    $(FMAP_CONSOLE_SIZE)), 0x10000)
-else
-FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \
-	$(FMAP_FMAP_SIZE)), 0x10000)
-endif
 FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
 FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
 else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
@@ -890,14 +882,18 @@
 endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)

#
+# X86 FMAP region
+#
+#
+# position, size
+FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE))
+FMAP_FMAP_SIZE := 0x200
+
+#
 # X86 COREBOOT default cbfs FMAP region
 #
 # position and size of CBFS, relative to BIOS_BASE
-ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
-else
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE))
-endif
+FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 else # ifeq ($(CONFIG_ARCH_X86),y)
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
index 1f1aa43..174db1f 100644
--- a/util/cbfstool/default-x86.fmd
+++ b/util/cbfstool/default-x86.fmd
@@ -9,9 +9,9 @@

FLASH@##ROM_BASE## ##ROM_SIZE## {
    BIOS@##BIOS_BASE## ##BIOS_SIZE## {
-		FMAP@##FMAP_BASE## ##FMAP_SIZE##
    	##CONSOLE_ENTRY##
    	##MRC_CACHE_ENTRY##
+		FMAP@##FMAP_BASE## ##FMAP_SIZE##
    	COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
    }
 }