Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44991 )
Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ......................................................................
cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK
The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are written to after the Lock bit is set; this is helpful with securing SMM.
BUG=b:164489598
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647 --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44991/1
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..6e30199 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -30,6 +30,7 @@
#define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +#define SMRR_PHYS_MASK_LOCK (1 << 10)
/* Specific to model_6fx and model_1067x */ #define MSR_SMRR_PHYS_BASE 0xa0
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44991 )
Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44991 )
Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44991 )
Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44991 )
Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ......................................................................
cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK
The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are written to after the Lock bit is set; this is helpful with securing SMM.
BUG=b:164489598
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Caveh Jalali: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..6e30199 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -30,6 +30,7 @@
#define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +#define SMRR_PHYS_MASK_LOCK (1 << 10)
/* Specific to model_6fx and model_1067x */ #define MSR_SMRR_PHYS_BASE 0xa0
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44991 )
Change subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/18093 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18092 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/18091 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18090 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/18089 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/18096 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/18095 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/18094
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Caveh Jalali (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)