Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38071 )
Change subject: mb/asus/p5ql-em/devicetree.cb: Do minor fixes ......................................................................
mb/asus/p5ql-em/devicetree.cb: Do minor fixes
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode.
Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p5ql-em/devicetree.cb 1 file changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/38071/1
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index fd0b103..ab9860b 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -18,7 +18,7 @@ device lapic 0 on end end chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end + device lapic 0xacac off end end end device domain 0 on # PCI domain @@ -41,10 +41,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,1,3,4,5 as slots. register "pcie_slot_implemented" = "0x3b"
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38071 )
Change subject: mb/asus/p5ql-em/devicetree.cb: Do minor fixes ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38071 )
Change subject: mb/asus/p5ql-em/devicetree.cb: Do minor fixes ......................................................................
mb/asus/p5ql-em/devicetree.cb: Do minor fixes
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode.
Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/asus/p5ql-em/devicetree.cb 1 file changed, 1 insertion(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index fd0b103..ab9860b 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -18,7 +18,7 @@ device lapic 0 on end end chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end + device lapic 0xacac off end end end device domain 0 on # PCI domain @@ -41,10 +41,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,1,3,4,5 as slots. register "pcie_slot_implemented" = "0x3b"
-
Angel Pons (Code Review) -
Nico Huber (Code Review)