Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46337 )
Change subject: soc/intel/broadwell: Sort SA registers in ascending order ......................................................................
soc/intel/broadwell: Sort SA registers in ascending order
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/include/soc/systemagent.h 1 file changed, 41 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46337/1
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 6f475a5..5a52590 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -29,8 +29,6 @@
#define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 #define GGC 0x50 /* GMCH Graphics Control */ #define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) @@ -45,6 +43,11 @@ #define DPR_EPM (1 << 2) #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
#define PAM0 0x80 #define PAM1 0x81 @@ -60,14 +63,7 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2)
-#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ #define REMAPBASE 0x90 /* Remap base. */ #define REMAPLIMIT 0x98 /* Remap limit. */ #define TOM 0xa0 /* Top of DRAM in memory controller space. */ @@ -78,6 +74,13 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define SKPAD 0xdc /* Scratchpad Data */
+#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + /* MCHBAR */
#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) @@ -88,7 +91,6 @@
#define MC_LOCK 0x50fc
-#define BIOS_RESET_CPL 0x5da8 #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 @@ -99,11 +101,38 @@
#define PCU_DDR_PTM_CTL 0x5880
-#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4
+#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 + +/* Errors are returned back in bits 7:0 */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 + +#define BIOS_RESET_CPL 0x5da8 + #define SAPMCTL 0x5f00
#define HDAUDRID 0x6008 @@ -115,29 +144,6 @@ #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc
-/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 -#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - /* System Agent identification */ u8 systemagent_revision(void);
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46337 )
Change subject: soc/intel/broadwell: Sort SA registers in ascending order ......................................................................
Patch Set 3: Code-Review+2
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46337
to look at the new patch set (#5).
Change subject: soc/intel/broadwell: Sort SA registers in ascending order ......................................................................
soc/intel/broadwell: Sort SA registers in ascending order
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/include/soc/systemagent.h 1 file changed, 24 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46337/5
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46337 )
Change subject: soc/intel/broadwell: Sort SA registers in ascending order ......................................................................
Patch Set 9: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46337 )
Change subject: soc/intel/broadwell: Sort SA registers in ascending order ......................................................................
soc/intel/broadwell: Sort SA registers in ascending order
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46337 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/include/soc/systemagent.h 1 file changed, 24 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index f81d5a0..3b56e9d 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -29,8 +29,6 @@
#define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 #define GGC 0x50 /* GMCH Graphics Control */ #define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) @@ -45,6 +43,11 @@ #define DPR_EPM (1 << 2) #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
#define PAM0 0x80 #define PAM1 0x81 @@ -60,14 +63,7 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2)
-#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ #define REMAPBASE 0x90 /* Remap base. */ #define REMAPLIMIT 0x98 /* Remap limit. */ #define TOM 0xa0 /* Top of DRAM in memory controller space. */ @@ -78,6 +74,13 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define SKPAD 0xdc /* Scratchpad Data */
+#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + /* MCHBAR */
#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) @@ -85,20 +88,23 @@ #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x)))
#define MCHBAR_PEI_VERSION 0x5034 -#define BIOS_RESET_CPL 0x5da8 + #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define MCH_PAIR 0x5418 #define GDXCBAR 0x5420
-#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4
-/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 #define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 @@ -108,7 +114,8 @@ #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 -/* Errors are returned back in bits 7:0. */ + +/* Errors are returned back in bits 7:0 */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 @@ -117,8 +124,8 @@ #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_RESET_CPL 0x5da8
/* System Agent identification */ u8 systemagent_revision(void);
-
Angel Pons (Code Review) -
Nico Huber (Code Review)