Change in coreboot[master]: mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56926 )

Change subject: mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled
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mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled

GPIO PM was disabled for brya to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. All devices currently tested on brya support 4us
long pulses. This change drops the GPIO PM override and re-enables
dynamic GPIO PM.

TEST=Boot brya to OS, ensure no TPM errors.

Signed-off-by: Meera Ravindranath 
Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 0 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 25b81eb..5265109 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -24,17 +24,6 @@
    # Enable heci communication
    register "HeciEnabled" = "1"

-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
-
    # Enable CNVi BT
    register "CnviBtCore" = "true"