[S] Change in coreboot[master]: src/soc/intel/alderlake: Add HDA link enable parameter

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68117 )

Change subject: src/soc/intel/alderlake: Add HDA link enable parameter
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src/soc/intel/alderlake: Add HDA link enable parameter

This patch adds HDA link enable parameter. The PchHDaAudioLinkHdaEnable
is required to be set for HDA link signals. The FSP uses it to enable
HDA SDI signal wake/response through HDA PCR registers. Otherwise, the
HDA link is not going to work even the HDA GPIO pins are configured
properly.

TEST=Add pch_hda_link_enable = "1" in devicetree & make & ensure the
     HDA ALC711 codec (HDA configured) is recognized on ADL-S RVP

Signed-off-by: Gaggery Tsai 
Change-Id: Id72cc9c3924250bd8f27174299a641c09c2dcad6
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 25 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/68117/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 4cb6066..50de43c 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -323,6 +323,7 @@

/* Audio related */
    uint8_t pch_hda_dsp_enable;
+	uint8_t pch_hda_link_enable;

/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
    enum {
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index c0bdb0d..d127f18 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -239,12 +239,12 @@
    m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
    m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
    /*
-	 * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
-	 * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
-	 * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
-	 * configuration for audio pads.
+	 * For HDA link, PchHdaAudioLinkHdaEnable needs to be set, FSP will set HDA PCR
+	 * to activate SDI wake/response. For Non-HDA linkgit statu, Mainboard is expected
+	 * to perform all GPIO configuration in coreboot and hence these UPDs are set
+	 * to 0 to skip FSP GPIO configuration for audio pads.
     */
-	m_cfg->PchHdaAudioLinkHdaEnable = 0;
+	m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_link_enable;
    memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
    memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
    memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));