Change in coreboot[master]: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 184 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/1
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 5e04c9a..9254bd6 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -18,6 +18,8 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> +#include <console/console.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> @@ -28,6 +30,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <soc/systemagent.h> #include <string.h> #include <wrdd.h>
@@ -190,6 +193,97 @@ return read32((void *)pmc_bar + IRQ_REG); }
+static unsigned long soc_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; + bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; + + if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 5, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* TCSS Thunderbolt root ports */ + for (int i = 0; i < 4; i++) { + uint64_t tbtbar = MCHBAR64(TBT0BAR + i*8) & VTBAR_MASK; + bool tbten = MCHBAR32(TBT0BAR + i*8) & VTBAR_ENABLED; + if (tbtbar && tbten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() -1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if we have VT-d capability + * and FSP does not override its feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + void acpi_create_gnvs(struct global_nvs_t *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index b3797c1..4f938fa 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -49,6 +49,27 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000
+#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfc000000 #define REG_BASE_SIZE 0x1000
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f54ab4b..2aa5d9e 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -43,6 +43,10 @@ #define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) #define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0)
+#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 56a2bd8..9b23a0b 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -34,10 +34,22 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23)
#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull
#define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -47,4 +59,21 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48
+static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + #endif diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 810cff4..bb9b7b7 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -14,9 +14,36 @@ */
#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> + +static void soc_fspm_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_tigerlake_dev_config *config) +{ + /* Vt-D config */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; +}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - /* TODO: Update with UPD override as FSP matures */ + const struct soc_intel_tigerlake_dev_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + config = config_of_soc(); + + soc_fspm_params(m_cfg, config); } + diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 9c8f645..cb9ea18 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -21,6 +21,7 @@
#include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/systemagent.h> @@ -56,6 +57,13 @@
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); }
/*
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/1/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/1/src/soc/intel/tigerlake/acp... PS1, Line 202: if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/38165/1/src/soc/intel/tigerlake/acp... PS1, Line 259: sa_get_gsm_base(), sa_get_tolud_base() -1); need consistent spacing around '-' (ctx:WxV)
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 183 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/2/src/soc/intel/tigerlake/acp... PS2, Line 202: if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/38165/2/src/soc/intel/tigerlake/acp... PS2, Line 259: sa_get_gsm_base(), sa_get_tolud_base() -1); need consistent spacing around '-' (ctx:WxV)
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 183 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/3
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 3:
(2 comments)
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/2/src/soc/intel/tigerlake/acp... PS2, Line 202: if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
suspect code indent for conditional statements (8, 8)
Done
https://review.coreboot.org/c/coreboot/+/38165/2/src/soc/intel/tigerlake/acp... PS2, Line 259: sa_get_gsm_base(), sa_get_tolud_base() -1);
need consistent spacing around '-' (ctx:WxV)
Done
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 169 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/4
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/systemagent.h:
https://review.coreboot.org/c/coreboot/+/38165/4/src/soc/intel/tigerlake/inc... PS4, Line 4: 2019 2019-2020. same for other files
https://review.coreboot.org/c/coreboot/+/38165/4/src/soc/intel/tigerlake/inc... PS4, Line 37: #define CAPID0_A 0xe4 : #define VTD_DISABLE (1 << 23) can we move common defines to the common header?
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 7 files changed, 173 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/5
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/systemagent.h:
https://review.coreboot.org/c/coreboot/+/38165/4/src/soc/intel/tigerlake/inc... PS4, Line 4: 2019
2019-2020. […]
done.
https://review.coreboot.org/c/coreboot/+/38165/4/src/soc/intel/tigerlake/inc... PS4, Line 37: #define CAPID0_A 0xe4 : #define VTD_DISABLE (1 << 23)
can we move common defines to the common header?
done.
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 172 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/6
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table.
BUG=None TEST=Booted to kernel and verified the DMAR table contents.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 173 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/7
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 7:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38165/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38165/7//COMMIT_MSG@10 PS7, Line 10: acpi ACPI
https://review.coreboot.org/c/coreboot/+/38165/7//COMMIT_MSG@13 PS7, Line 13: TEST=Booted to kernel and verified the DMAR table contents. How did you verify it?
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 243: int unsigned
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 244: i*8 Please add spaces around operators (also below).
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 259: sa_get_gsm_base(), sa_get_tolud_base() - 1); Should fit in 96 characters?
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 273: */ Please use allowed comment styles [1], and reflow for 96 characters.
[1]: https://doc.coreboot.org/coding_style.html#commenting
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 280: soc_fill_dmar); Fits in 96 characters?
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#8).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table.
BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 173 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/8
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 8:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38165/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38165/7//COMMIT_MSG@10 PS7, Line 10: acpi
ACPI
Ack
https://review.coreboot.org/c/coreboot/+/38165/7//COMMIT_MSG@13 PS7, Line 13: TEST=Booted to kernel and verified the DMAR table contents.
How did you verify it?
Done
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 243: int
unsigned
Ack
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 244: i*8
Please add spaces around operators (also below).
Ack
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 259: sa_get_gsm_base(), sa_get_tolud_base() - 1);
Should fit in 96 characters?
no, it does not fit as total 97 characters.
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 273: */
Please use allowed comment styles [1], and reflow for 96 characters. […]
Ack
https://review.coreboot.org/c/coreboot/+/38165/7/src/soc/intel/tigerlake/acp... PS7, Line 280: soc_fill_dmar);
Fits in 96 characters?
Ack
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 9: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/38165/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38165/9//COMMIT_MSG@9 PS9, Line 9: Tigerlake Tiger Lake
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/acp... PS9, Line 259: sa_get_gsm_base(), sa_get_tolud_base() - 1); Does this fit into 96 characters?
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/sys... File src/soc/intel/tigerlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/sys... PS9, Line 66: ARRAY_SIZE(soc_vtd_resources)); Does this fit into 96 characters?
Hello build bot (Jenkins), Nico Huber, Paul Menzel, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#10).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tiger Lake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table.
BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 173 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/10
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38165/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38165/9//COMMIT_MSG@9 PS9, Line 9: Tigerlake
Tiger Lake
Ack
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/acp... PS9, Line 259: sa_get_gsm_base(), sa_get_tolud_base() - 1);
Does this fit into 96 characters?
Total 97 characters, it does not fit.
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/sys... File src/soc/intel/tigerlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/sys... PS9, Line 66: ARRAY_SIZE(soc_vtd_resources));
Does this fit into 96 characters?
Total 98 characters, it does not fit.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 10: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 10: Code-Review-1
can you please hold off submitting this? I don't think we should be just unconditionally enabling thunderbolt ports. adding some more folks to take a look.
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/10/src/soc/intel/tigerlake/ac... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/10/src/soc/intel/tigerlake/ac... PS10, Line 198: struct device *const did you mean const struct device *?
const struct device *const would also be OK.
same with ipu_dev.
https://review.coreboot.org/c/coreboot/+/38165/10/src/soc/intel/tigerlake/ac... PS10, Line 243: 4 do we have a constant for the number of TCSS ports? maybe add to tigerlake/chip.h?
Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Wonkyu Kim, caveh jalali, Paul Menzel, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38165
to look at the new patch set (#11).
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table.
BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 174 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/11
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/10/src/soc/intel/tigerlake/ac... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/10/src/soc/intel/tigerlake/ac... PS10, Line 198: struct device *const
did you mean […]
Ack
https://review.coreboot.org/c/coreboot/+/38165/10/src/soc/intel/tigerlake/ac... PS10, Line 243: 4
do we have a constant for the number of TCSS ports? […]
Ack by adding MAX_TBT_PCIE_PORT into /include/soc/systemagent.h
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 11:
Can you add topic?
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 11:
Patch Set 11:
Can you add topic?
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/acp... PS9, Line 259: sa_get_gsm_base(), sa_get_tolud_base() - 1);
Total 97 characters, it does not fit.
Done
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/sys... File src/soc/intel/tigerlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38165/9/src/soc/intel/tigerlake/sys... PS9, Line 66: ARRAY_SIZE(soc_vtd_resources));
Total 98 characters, it does not fit.
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 11: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table.
BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao john.zhao@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 174 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index b9cae3c..af4076c 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -18,6 +18,8 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> +#include <console/console.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> @@ -191,6 +193,98 @@ return read32((void *)pmc_bar + IRQ_REG); }
+static unsigned long soc_fill_dmar(unsigned long current) +{ + const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; + bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; + + if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 5, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* TCSS Thunderbolt root ports */ + for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { + uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK; + bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED; + if (tbtbar && tbten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + void acpi_create_gnvs(struct global_nvs_t *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index f403873..d9fc01e 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -51,6 +51,27 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000
+#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfb000000 #define REG_BASE_SIZE 0x1000
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index ef2dfe3..af449ba 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -53,6 +53,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
+#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 56a2bd8..92d7072 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,10 +34,23 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23)
#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull
#define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -47,4 +60,21 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48
+static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + #endif diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 4b9b007..072c99e 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -131,6 +131,20 @@ m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + + /* Vt-D config */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 9c8f645..152f8f9 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,7 @@
#include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/systemagent.h> @@ -56,6 +57,13 @@
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); }
/*
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38165 )
Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ......................................................................
Patch Set 12:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1328 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1327 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1326
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
build bot (Jenkins) (Code Review)
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caveh jalali (Code Review)
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Furquan Shaikh (Code Review)
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John Zhao (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Pratikkumar V Prajapati (Code Review)
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Wonkyu Kim (Code Review)