Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

[Shreesh Chhabbi (Code Review)]

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
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Patch Set 38:

(1 comment)

File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49766/comment/b312fadd_7f9e4ff2 
PS37, Line 77: S0i3.2
> @Shreesh, my mistake. S0i3.2 will get disable as part of CNVi check only.

Ok updated the code back. :)