Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32031
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
chromeos: update old boards to use lb_add_gpios notation
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone.
BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching kitching@google.com --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 11 files changed, 155 insertions(+), 369 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32031/1
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 11b28cd..a956e28 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -33,53 +33,28 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO active Low */ + {WP_GPIO, ACTIVE_LOW, !get_write_protect_state(), + "write protect"},
- int lidswitch = 0; - if (!gpio_base) - return; + /* Recovery: virtual GPIO active high */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + /* lid switch value from EC */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Write Protect: GPIO active Low */ - gpios->gpios[0].port = WP_GPIO; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Power Button - Hardcode Low as power button may still be + * pressed when read here.*/ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Recovery: virtual GPIO active high */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* lid switch value from EC */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); - printk(BIOS_DEBUG,"LID SWITCH FROM EC: %x\n", lidswitch); - - /* Power Button - Hardcode Low as power button may still be pressed - when read here.*/ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - + /* Was VGA Option ROM loaded? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index ae456b4..65139bb 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -25,44 +25,21 @@
void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low (WP_GPIO) */ + {EXYNOS5_GPD1, ACTIVE_LOW, gpio_get_value(GPIO_D16), + "write protect"},
- /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active low */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* Lid: active high (LID_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"},
- /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* Power: virtual GPIO active low (POWER_GPIO) */ + {EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X13), "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 4cf2a85..024fd4c 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -24,46 +24,21 @@
void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - /* TBD(twarren@nvidia.com): Any analogs for these on Foster-FFD? */ + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low */ + {-1, ACTIVE_LOW, get_write_protect_state(), "write protect"},
- /* Write Protect: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active high */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* TODO: Power: active low / high depending on board id */ + {GPIO(X5), ACTIVE_LOW, -1, "power"},
- /* TODO: Power: active low / high depending on board id */ - gpios->gpios[count].port = GPIO(X5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* TODO: Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* TODO: Reset: active low (output) */ + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 335f1f7..5156404 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -22,43 +22,28 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO57 = PCH_SPI_WP_D */ + {57, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
- /* Write Protect: GPIO57 = PCH_SPI_WP_D */ - gpios->gpios[0].port = 57; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - /* Recovery: the "switch" comes from the EC */ - gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Recovery: the "switch" comes from the EC */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Lid: the "switch" comes from the EC */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_lid_switch(); - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Lid: the "switch" comes from the EC */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Power Button: hard-coded as not pressed; we'll detect later presses - * via SMI. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 0; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); + /* Power Button: hard-coded as not pressed; we'll detect later + * presses via SMI. */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 1420bf5..ede600c 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -30,8 +30,6 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -41,39 +39,24 @@ if (!gpio_base) return;
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO70 active high */ + {70, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
- /* Write Protect: GPIO70 active high */ - gpios->gpios[0].port = 70; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); + /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Lid switch GPIO active high (open). */ + {15, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Lid switch GPIO active high (open). */ - gpios->gpios[3].port = 15; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
- /* Power Button */ - gpios->gpios[4].port = 101; - gpios->gpios[4].polarity = ACTIVE_LOW; - gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index e782986..6f3b8b7 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -25,44 +25,20 @@
void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low (WP_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_LOW, gpio_get_value(GPIO_X30), "write protect"},
- /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active low */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* Lid: active high (LID_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X34), "lid"},
- /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X12); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* Power: virtual GPIO active low (POWER_GPIO) */ + {EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X12), "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index d366e40..015e0aa 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -29,49 +29,30 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 7 - void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO7 */ + {7, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
- /* Write Protect: GPIO7 */ - gpios->gpios[0].port = 7; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: Virtual switch */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: Virtual switch */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Lid Switch: Virtual switch */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Lid Switch: Virtual switch */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button: Virtual switch */ + /* Hard-code value to de-asserted */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Power Button: Virtual switch */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; /* Hard-code to de-asserted */ - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); + /* Was VGA Option ROM loaded? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - - /* EC is in RW mode when it isn't in recovery mode. */ - gpios->gpios[6].port = -1; - gpios->gpios[6].polarity = ACTIVE_HIGH; - gpios->gpios[6].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[6].name,"ec_in_rw", GPIO_MAX_NAME_LENGTH); + /* EC is in RW mode when it isn't in recovery mode. */ + {-1, ACTIVE_HIGH, !get_recovery_mode_switch(), "ec_in_rw"} + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 1c62e5e..f38f6d4 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -26,8 +26,6 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -39,39 +37,23 @@ u32 gp_lvl = inl(gpio_base + GP_LVL); u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO22 */ + {0, ACTIVE_LOW, (gp_lvl >> 22) & 1, "write protect"},
- /* Write Protect: GPIO22 */ - gpios->gpios[0].port = 0; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl >> 22) & 1; - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ + {69, ACTIVE_HIGH, (gp_lvl3 >> (69-64)) & 1, "recovery"},
- /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - gpios->gpios[1].port = 69; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1; - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {-1, ACTIVE_HIGH, 1, "lid"},
- /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Power Button */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA option ROM? */ - gpios->gpios[5].port = -1; - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA option ROM? */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 8c0aeea..31efe29 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -26,8 +26,6 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -40,39 +38,23 @@ u32 gp_lvl2 = inl(gpio_base + 0x38); /* u32 gp_lvl3 = inl(gpio_base + 0x48); */
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO48 */ + {48, ACTIVE_LOW, (gp_lvl2 >> (48-32)) & 1, "write protect"},
- /* Write Protect: GPIO48 */ - gpios->gpios[0].port = 48; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1; - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO22 */ + {22, ACTIVE_LOW, (gp_lvl >> 22) & 1, "recovery"},
- /* Recovery: GPIO22 */ - gpios->gpios[1].port = 22; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = (gp_lvl >> 22) & 1; - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {-1, ACTIVE_HIGH, 1, "lid"},
- /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Power Button */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA option ROM? */ - gpios->gpios[5].port = -1; - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA option ROM? */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 5d688fe..2d4fb61 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -34,46 +34,31 @@ #include "ec.h" #include <ec/smsc/mec1308/ec.h>
-#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); - u8 lid = ec_read(0x83); + u8 lid = ec_read(0x83);
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO24 = KBC3_SPI_WP# */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"},
- /* Write Protect: GPIO24 = KBC3_SPI_WP# */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"},
- /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + {100, ACTIVE_HIGH, lid & 1, "lid"},
- gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = lid & 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
- /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 295c31f..b1ad137 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -31,46 +31,31 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO68 = CHP3_SPI_WP */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"},
- /* Write Protect: GPIO68 = CHP3_SPI_WP */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"},
- /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {100, ACTIVE_HIGH, 1, "lid"},
- /* Hard code the lid switch GPIO to open. */ - gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
- /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32031/1/src/mainboard/google/peach_pit/chrom... File src/mainboard/google/peach_pit/chromeos.c:
https://review.coreboot.org/#/c/32031/1/src/mainboard/google/peach_pit/chrom... PS1, Line 30: {EXYNOS5_GPX3, ACTIVE_LOW, gpio_get_value(GPIO_X30), "write protect"}, line over 80 characters
Hello Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32031
to look at the new patch set (#2).
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
chromeos: update old boards to use lb_add_gpios notation
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone.
BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching kitching@google.com --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 11 files changed, 156 insertions(+), 369 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32031/2
Joel Kitching has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32031/1/src/mainboard/google/peach_pit/chrom... File src/mainboard/google/peach_pit/chromeos.c:
https://review.coreboot.org/#/c/32031/1/src/mainboard/google/peach_pit/chrom... PS1, Line 30: {EXYNOS5_GPX3, ACTIVE_LOW, gpio_get_value(GPIO_X30), "write protect"},
line over 80 characters
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 2:
(9 comments)
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/parrot/chromeos... File src/mainboard/google/parrot/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/parrot/chromeos... PS2, Line 39: if (!gpio_base) I don't see gpio_base used here.
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... File src/mainboard/intel/baskingridge/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... PS2, Line 32: u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; I think we should have global declarations for things like pm_base() and gpio_base()... Not something you would fix here though.
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... PS2, Line 42: {0, ACTIVE_LOW, (gp_lvl >> 22) & 1, "write protect"}, Complete get_write_protect_state() implementation below instead?
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... PS2, Line 45: {69, ACTIVE_HIGH, (gp_lvl3 >> (69-64)) & 1, "recovery"}, Use get_recovery_mode_switch() ?
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... File src/mainboard/intel/emeraldlake2/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 38: u32 gp_lvl2 = inl(gpio_base + 0x38); GP_LVL==0x0c, GP_LVL3==0x38
But I think this function can be written without gpio_base(), see below.
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 43: {48, ACTIVE_LOW, (gp_lvl2 >> (48-32)) & 1, "write protect"}, Implement get_write_protect_state() ?
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 46: {22, ACTIVE_LOW, (gp_lvl >> 22) & 1, "recovery"}, Use get_recovery_mode_switch() ?
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 69: CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME), Looks like phys dev switch?
https://review.coreboot.org/#/c/32031/2/src/mainboard/samsung/lumpy/chromeos... File src/mainboard/samsung/lumpy/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/samsung/lumpy/chromeos... PS2, Line 101: pci_write_config32(dev, SATA_SP, flags); Just curious, why do we stash the GPIO states here? Looked like some other boards do not.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 2:
(2 comments)
LGTM but Kyösti made some good suggestions.
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/butterfly/chrom... File src/mainboard/google/butterfly/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/butterfly/chrom... PS2, Line 39: /* Write Protect: GPIO active Low */ nit: not sure if we still need these comments everywhere because with the shorter notation it's all pretty self-explanatory
https://review.coreboot.org/#/c/32031/2/src/mainboard/samsung/lumpy/chromeos... File src/mainboard/samsung/lumpy/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/samsung/lumpy/chromeos... PS2, Line 101: pci_write_config32(dev, SATA_SP, flags);
Just curious, why do we stash the GPIO states here? Looked like some other boards do not.
No idea... Lumpy is a really old board, quite possible this is no longer used but probably not worth worrying about.
Hello Kyösti Mälkki, Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32031
to look at the new patch set (#4).
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
chromeos: update old boards to use lb_add_gpios notation
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone.
BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching kitching@google.com --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 11 files changed, 156 insertions(+), 369 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32031/4
Hello Kyösti Mälkki, Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32031
to look at the new patch set (#5).
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
chromeos: update old boards to use lb_add_gpios notation
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone.
BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching kitching@google.com --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 11 files changed, 164 insertions(+), 393 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32031/5
Joel Kitching has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 5: Code-Review+1
(10 comments)
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/butterfly/chrom... File src/mainboard/google/butterfly/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/butterfly/chrom... PS2, Line 39: /* Write Protect: GPIO active Low */
nit: not sure if we still need these comments everywhere because with the shorter notation it's all […]
I think I'd like to preserve them here for posterity's sake - we can clean them up / remove them in another CL if we wish.
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/parrot/chromeos... File src/mainboard/google/parrot/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/google/parrot/chromeos... PS2, Line 39: if (!gpio_base)
I don't see gpio_base used here.
Done
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... File src/mainboard/intel/baskingridge/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... PS2, Line 32: u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
I think we should have global declarations for things like pm_base() and gpio_base()... […]
What other kinds of places are they used? But yeah, probably can work on that separately.
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... PS2, Line 42: {0, ACTIVE_LOW, (gp_lvl >> 22) & 1, "write protect"},
Complete get_write_protect_state() implementation below instead?
Done
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/baskingridge/chr... PS2, Line 45: {69, ACTIVE_HIGH, (gp_lvl3 >> (69-64)) & 1, "recovery"},
Use get_recovery_mode_switch() ?
Done
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... File src/mainboard/intel/emeraldlake2/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 38: u32 gp_lvl2 = inl(gpio_base + 0x38);
GP_LVL==0x0c, GP_LVL3==0x38 […]
Done
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 43: {48, ACTIVE_LOW, (gp_lvl2 >> (48-32)) & 1, "write protect"},
Implement get_write_protect_state() ?
Done
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 46: {22, ACTIVE_LOW, (gp_lvl >> 22) & 1, "recovery"},
Use get_recovery_mode_switch() ?
Done
https://review.coreboot.org/#/c/32031/2/src/mainboard/intel/emeraldlake2/chr... PS2, Line 69: CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME),
Looks like phys dev switch?
Will remove this in a subsequent CL.
https://review.coreboot.org/#/c/32031/2/src/mainboard/samsung/lumpy/chromeos... File src/mainboard/samsung/lumpy/chromeos.c:
https://review.coreboot.org/#/c/32031/2/src/mainboard/samsung/lumpy/chromeos... PS2, Line 101: pci_write_config32(dev, SATA_SP, flags);
No idea... […]
Ack
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 5: Code-Review+1
Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32031/5/src/mainboard/google/butterfly/chrom... File src/mainboard/google/butterfly/chromeos.c:
https://review.coreboot.org/#/c/32031/5/src/mainboard/google/butterfly/chrom... PS5, Line 55: - Suggestion for later: Add an enum for this value like GPIO_PSEUDO
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32031 )
Change subject: chromeos: update old boards to use lb_add_gpios notation ......................................................................
chromeos: update old boards to use lb_add_gpios notation
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone.
BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching kitching@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Julius Werner jwerner@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 11 files changed, 164 insertions(+), 393 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved Simon Glass: Looks good to me, but someone else must approve Joel Kitching: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 11b28cd..a956e28 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -33,53 +33,28 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO active Low */ + {WP_GPIO, ACTIVE_LOW, !get_write_protect_state(), + "write protect"},
- int lidswitch = 0; - if (!gpio_base) - return; + /* Recovery: virtual GPIO active high */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + /* lid switch value from EC */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Write Protect: GPIO active Low */ - gpios->gpios[0].port = WP_GPIO; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Power Button - Hardcode Low as power button may still be + * pressed when read here.*/ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Recovery: virtual GPIO active high */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* lid switch value from EC */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); - printk(BIOS_DEBUG,"LID SWITCH FROM EC: %x\n", lidswitch); - - /* Power Button - Hardcode Low as power button may still be pressed - when read here.*/ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - + /* Was VGA Option ROM loaded? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index ae456b4..65139bb 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -25,44 +25,21 @@
void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low (WP_GPIO) */ + {EXYNOS5_GPD1, ACTIVE_LOW, gpio_get_value(GPIO_D16), + "write protect"},
- /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active low */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* Lid: active high (LID_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"},
- /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* Power: virtual GPIO active low (POWER_GPIO) */ + {EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X13), "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 4cf2a85..024fd4c 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -24,46 +24,21 @@
void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - /* TBD(twarren@nvidia.com): Any analogs for these on Foster-FFD? */ + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low */ + {-1, ACTIVE_LOW, get_write_protect_state(), "write protect"},
- /* Write Protect: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active high */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* TODO: Power: active low / high depending on board id */ + {GPIO(X5), ACTIVE_LOW, -1, "power"},
- /* TODO: Power: active low / high depending on board id */ - gpios->gpios[count].port = GPIO(X5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* TODO: Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* TODO: Reset: active low (output) */ + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 335f1f7..5156404 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -22,43 +22,28 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO57 = PCH_SPI_WP_D */ + {57, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
- /* Write Protect: GPIO57 = PCH_SPI_WP_D */ - gpios->gpios[0].port = 57; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - /* Recovery: the "switch" comes from the EC */ - gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Recovery: the "switch" comes from the EC */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Lid: the "switch" comes from the EC */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_lid_switch(); - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Lid: the "switch" comes from the EC */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Power Button: hard-coded as not pressed; we'll detect later presses - * via SMI. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 0; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); + /* Power Button: hard-coded as not pressed; we'll detect later + * presses via SMI. */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 1420bf5..99fc764 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -30,50 +30,29 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
- if (!gpio_base) - return; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO70 active high */ + {70, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Write Protect: GPIO70 active high */ - gpios->gpios[0].port = 70; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); + /* Lid switch GPIO active high (open). */ + {15, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
- /* Lid switch GPIO active high (open). */ - gpios->gpios[3].port = 15; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); - - /* Power Button */ - gpios->gpios[4].port = 101; - gpios->gpios[4].polarity = ACTIVE_LOW; - gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index e782986..f507bd8 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -25,44 +25,21 @@
void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low (WP_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_LOW, gpio_get_value(GPIO_X30), + "write protect"},
- /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active low */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* Lid: active high (LID_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X34), "lid"},
- /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X12); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* Power: virtual GPIO active low (POWER_GPIO) */ + {EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X12), "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index d366e40..015e0aa 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -29,49 +29,30 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 7 - void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO7 */ + {7, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
- /* Write Protect: GPIO7 */ - gpios->gpios[0].port = 7; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: Virtual switch */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- /* Recovery: Virtual switch */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Lid Switch: Virtual switch */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- /* Lid Switch: Virtual switch */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button: Virtual switch */ + /* Hard-code value to de-asserted */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Power Button: Virtual switch */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; /* Hard-code to de-asserted */ - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); + /* Was VGA Option ROM loaded? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - - /* EC is in RW mode when it isn't in recovery mode. */ - gpios->gpios[6].port = -1; - gpios->gpios[6].polarity = ACTIVE_HIGH; - gpios->gpios[6].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[6].name,"ec_in_rw", GPIO_MAX_NAME_LENGTH); + /* EC is in RW mode when it isn't in recovery mode. */ + {-1, ACTIVE_HIGH, !get_recovery_mode_switch(), "ec_in_rw"} + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 1c62e5e..875578f 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -26,52 +26,25 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO22 */ + {0, ACTIVE_LOW, get_write_protect_state(), "write protect"},
- if (!gpio_base) - return; + /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ + {69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- u32 gp_lvl = inl(gpio_base + GP_LVL); - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); + /* Hard code the lid switch GPIO to open. */ + {-1, ACTIVE_HIGH, 1, "lid"},
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + /* Power Button */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Write Protect: GPIO22 */ - gpios->gpios[0].port = 0; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl >> 22) & 1; - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - - /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - gpios->gpios[1].port = 69; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1; - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); - - /* Power Button */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA option ROM? */ - gpios->gpios[5].port = -1; - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA option ROM? */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
@@ -86,7 +59,8 @@
int get_write_protect_state(void) { - return 0; + /* Write protect is active low, so invert it here */ + return !get_gpio(22); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 8c0aeea..9fae822 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -26,53 +26,25 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO48 */ + {48, ACTIVE_LOW, get_write_protect_state(), "write protect"},
- if (!gpio_base) - return; + /* Recovery: GPIO22 */ + {22, ACTIVE_LOW, get_recovery_mode_switch(), "recovery"},
- u32 gp_lvl = inl(gpio_base + 0x0c); - u32 gp_lvl2 = inl(gpio_base + 0x38); - /* u32 gp_lvl3 = inl(gpio_base + 0x48); */ + /* Hard code the lid switch GPIO to open. */ + {-1, ACTIVE_HIGH, 1, "lid"},
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + /* Power Button */ + {-1, ACTIVE_HIGH, 0, "power"},
- /* Write Protect: GPIO48 */ - gpios->gpios[0].port = 48; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1; - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - - /* Recovery: GPIO22 */ - gpios->gpios[1].port = 22; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = (gp_lvl >> 22) & 1; - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); - - /* Power Button */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA option ROM? */ - gpios->gpios[5].port = -1; - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA option ROM? */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
@@ -82,6 +54,12 @@ return !get_gpio(22); }
+int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !get_gpio(48); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 5d688fe..2d4fb61 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -34,46 +34,31 @@ #include "ec.h" #include <ec/smsc/mec1308/ec.h>
-#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); - u8 lid = ec_read(0x83); + u8 lid = ec_read(0x83);
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO24 = KBC3_SPI_WP# */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"},
- /* Write Protect: GPIO24 = KBC3_SPI_WP# */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"},
- /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + {100, ACTIVE_HIGH, lid & 1, "lid"},
- gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = lid & 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
- /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 295c31f..b1ad137 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -31,46 +31,31 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
-#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO68 = CHP3_SPI_WP */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"},
- /* Write Protect: GPIO68 = CHP3_SPI_WP */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"},
- /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {100, ACTIVE_HIGH, 1, "lid"},
- /* Hard code the lid switch GPIO to open. */ - gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
- /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif
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