Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63399 )
Change subject: [WIP]soc/intel/cannonlake: Don't use __SIMPLE_DEVICE__ ......................................................................
[WIP]soc/intel/cannonlake: Don't use __SIMPLE_DEVICE__
Change-Id: I3c4096783695440911c09c59d8f9ca825136bf1b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/include/device/pnp_type.h M src/include/rules.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/smbus/smbus_early.c M src/superio/aspeed/common/early_config.c 9 files changed, 53 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63399/1
diff --git a/src/include/device/pnp_type.h b/src/include/device/pnp_type.h index f0d36bd..cffc28d 100644 --- a/src/include/device/pnp_type.h +++ b/src/include/device/pnp_type.h @@ -9,7 +9,7 @@
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-#if defined(__SIMPLE_DEVICE__) +#if !ENV_RAMSTAGE #define ENV_PNP_SIMPLE_DEVICE 1 #else #define ENV_PNP_SIMPLE_DEVICE 0 diff --git a/src/include/rules.h b/src/include/rules.h index a7642ec..6c79196 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -321,7 +321,7 @@ * be built with simple device model. */
-#if !ENV_RAMSTAGE && !CONFIG(NO_EARLY_SIMPLE_DEVICE) +#if !ENV_RAMSTAGE && (!CONFIG(NO_EARLY_SIMPLE_DEVICE) || ENV_SMM || defined(__ACPI__)) #define __SIMPLE_DEVICE__ #endif
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0a61381..9c5dcb2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -114,6 +114,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select NO_EARLY_SIMPLE_DEVICE
config MAX_CPUS int diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 578cbbf..3f9ef2b 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include "device/device.h" #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> @@ -156,12 +157,12 @@
};
-static uint8_t get_dev_revision(pci_devfn_t dev) +static uint8_t get_dev_revision(const struct device *dev) { return pci_read_config8(dev, PCI_REVISION_ID); }
-static uint16_t get_dev_id(pci_devfn_t dev) +static uint16_t get_dev_id(const struct device *dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } @@ -201,7 +202,7 @@ static void report_mch_info(void) { int i; - pci_devfn_t dev = SA_DEV_ROOT; + const struct device *dev = SA_DEV_ROOT; uint16_t mchid = get_dev_id(dev); uint8_t mch_revision = get_dev_revision(dev); const char *mch_type = "Unknown"; @@ -220,7 +221,7 @@ static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_LPC; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown";
@@ -237,7 +238,7 @@ static void report_igd_info(void) { int i; - pci_devfn_t dev = SA_DEV_IGD; + const struct device *dev = SA_DEV_IGD; uint16_t igdid = get_dev_id(dev); const char *igd_type = "Unknown";
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 6998eb1..0f1bded 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -20,19 +20,32 @@ #define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) #if defined(__SIMPLE_DEVICE__) #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#else +#define SA_DEV_ROOT __pci_0_00_0 #endif
#define SA_DEV_SLOT_PEG 0x01 #define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) #define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) -#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#if defined(__SIMPLE_DEVICE__) #define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0) #define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1) -#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) +#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) +#else +#define SA_DEV_PEG0 __pci_0_01_0 +#define SA_DEV_PEG1 __pci_0_01_1 +#define SA_DEV_PEG2 __pci_0_01_2 + +#endif
#define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) -#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#else +#define SA_DEV_IGD __pci_0_02_0 +#endif
#define SA_DEV_SLOT_TS 0x04 #define SA_DEVFN_TS PCI_DEVFN(SA_DEV_SLOT_TS, 0) @@ -202,6 +215,6 @@ #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7)
#endif diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 395a14d..5bb9014 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -132,6 +132,22 @@ PCI_COMMAND_MASTER); }
+#else + +static uintptr_t gspi_get_base_addr(int devfn, const struct device *dev) +{ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void gspi_set_base_addr(int devfn, const struct device *dev, uintptr_t base) +{ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); +} + +#endif + void gspi_early_bar_init(void) { unsigned int gspi_bus; @@ -142,15 +158,13 @@
assert(gspi_max != 0); if (!cfg) { - printk(BIOS_ERR, "%s: No GSPI config provided by SoC!\n", - __func__); + printk(BIOS_ERR, "%s: No GSPI config provided by SoC!\n", __func__); return; }
gspi_base_addr = gspi_get_early_base(); if (!gspi_base_addr) { - printk(BIOS_ERR, "%s: GSPI base address provided is NULL!\n", - __func__); + printk(BIOS_ERR, "%s: GSPI base address provided is NULL!\n", __func__); return; }
@@ -158,26 +172,10 @@ if (!cfg[gspi_bus].early_init) continue; devfn = gspi_soc_bus_to_devfn(gspi_bus); - gspi_set_base_addr(devfn, NULL, - GSPI_BUS_BASE(gspi_base_addr, gspi_bus)); + gspi_set_base_addr(devfn, NULL, GSPI_BUS_BASE(gspi_base_addr, gspi_bus)); } }
-#else - -static uintptr_t gspi_get_base_addr(int devfn, struct device *dev) -{ - return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); -} - -static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base) -{ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); -} - -#endif
static int gspi_read_bus_range(unsigned int *start, unsigned int *end) { diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index c359417..91b5bd1 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -38,7 +38,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; - pci_devfn_t dev; + const struct device *dev; int devfn; uintptr_t base;
@@ -50,7 +50,7 @@ }
/* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + dev = pcidev_path_on_root(devfn);
/* Skip if not enabled for early init */ config = dw_i2c_get_soc_cfg(bus); @@ -69,7 +69,7 @@ lpss_reset_release(base);
/* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(dev->path.pci.devfn, STATE_D0);
/* Initialize the controller */ if (dw_i2c_init(bus, config) != CB_SUCCESS) { @@ -83,7 +83,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus) { int devfn; - pci_devfn_t dev; + const struct device *dev; uintptr_t base;
/* Find device+function for this controller */ @@ -92,7 +92,7 @@ return (uintptr_t)NULL;
/* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + dev = pcidev_path_on_root(devfn);
/* Read the first base address for this device */ base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index a3173f3..bddb626 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -10,7 +10,7 @@
void smbus_common_init(void) { - const pci_devfn_t dev = PCH_DEV_SMBUS; + const struct device *dev = PCH_DEV_SMBUS;
/* Set SMBus I/O base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_4, SMBUS_IO_BASE); diff --git a/src/superio/aspeed/common/early_config.c b/src/superio/aspeed/common/early_config.c index 716a896..79bdd11 100644 --- a/src/superio/aspeed/common/early_config.c +++ b/src/superio/aspeed/common/early_config.c @@ -11,6 +11,7 @@ uint32_t data = 0; uint8_t tmp; pnp_devfn_t dev = PNP_DEV(port, LDN_ILPC2AHB); + //const struct device *dev = dev_find_slot_pnp(port, LDN_ILPC2AHB);
pnp_enter_conf_state(dev); pnp_set_logical_device(dev);
-
Arthur Heymans (Code Review)