Change in coreboot[master]: sb/amd/common: Add alink.[ch] - coreboot-gerrit

1 Mar 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39186 )
Change subject: sb/amd/common: Add alink.[ch]
......................................................................
sb/amd/common: Add alink.[ch]
Change-Id: I6288adb31769cd4615e2d346bc427a73381c4585
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
A src/southbridge/amd/common/Kconfig
M src/southbridge/amd/common/Makefile.inc
A src/southbridge/amd/common/alink.c
A src/southbridge/amd/common/alink.h
4 files changed, 155 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39186/1

diff --git a/src/southbridge/amd/common/Kconfig b/src/southbridge/amd/common/Kconfig
new file mode 100644
index 0000000..b4610bd
--- /dev/null
+++ b/src/southbridge/amd/common/Kconfig
@@ -0,0 +1,5 @@
+config OUTHBRIDGE_AMD_COMMON_ALINK
+	bool
+	default n
+	help
+	  Select this option to access the FCH A-link configuration registers.
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
index dcebdb5..c5e7ac5 100644
--- a/src/southbridge/amd/common/Makefile.inc
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -5,3 +5,11 @@
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += amd_pci_util.c
+
+bootblock-$(CONFIG_SOUTHBRIDGE_AMD_COMMON_ALINK) += alink.c
+verstage-$(CONFIG_SOUTHBRIDGE_AMD_COMMON_ALINK) += alink.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_COMMON_ALINK) += alink.c
+postcar-$(CONFIG_SOUTHBRIDGE_AMD_COMMON_ALINK) += alink.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_COMMON_ALINK) += alink.c
+smm-$(CONFIG_SOUTHBRIDGE_AMD_COMMON_ALINK) += alink.c
+
diff --git a/src/southbridge/amd/common/alink.c b/src/southbridge/amd/common/alink.c
new file mode 100644
index 0000000..99ced3e
--- /dev/null
+++ b/src/southbridge/amd/common/alink.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <stdint.h>
+#include "alink.h"
+
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	// printk(BIOS_DEBUG, "about write %x, index=%x", tmp,
+	//				(reg_space&0x3)<<29 | reg_addr);
+
+	/* probably we don't have to do it again. */
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+}
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp,
+	//		(reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
+
+	/* probably we don't have to do it again. */
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+}
+
+/*
+ * space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	/* read axindc to tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	tmp = inl(AB_DATA);
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* write tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+}
diff --git a/src/southbridge/amd/common/alink.h b/src/southbridge/amd/common/alink.h
new file mode 100644
index 0000000..ca4bbd3d
--- /dev/null
+++ b/src/southbridge/amd/common/alink.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SB_AMD_COMMON_SMBUS_H
+#define SB_AMD_COMMON_SMBUS_H
+
+#include <stdint.h>
+
+#define AB_INDX				0xcd8
+#define AB_DATA				(AB_INDX + 4)
+
+#define AX_INDXC			0
+#define AX_INDXP			2
+#define AXCFG				4
+#define ABCFG				6
+#define RC_INDXC			1
+#define RC_INDXP			3
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)		\
+	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /* c or p? */, u32 axindc, u32 mask, u32 val);
+
+#endif
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/39186
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6288adb31769cd4615e2d346bc427a73381c4585
Gerrit-Change-Number: 39186
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr
Gerrit-MessageType: newchange



    