Cole Nelson has uploaded this change for review. ( https://review.coreboot.org/27019
Change subject: soc/intel/{glk,apl}: ensure C1E is disabled after S3 resume ......................................................................
soc/intel/{glk,apl}: ensure C1E is disabled after S3 resume
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume.
Disable C1E for GLK as it is for APL. This gives a coherent state before and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc' after boot and S3 resume.
Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10 Signed-off-by: Cole Nelson colex.nelson@intel.com --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/include/intelblocks/msr.h 2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/27019/1
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 4a7e40a..9337eb3 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,11 +53,11 @@ /* Power Management I/O base address for I/O trapping to C-states */ REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), /* Disable support for MONITOR and MWAIT instructions */ REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), #endif + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), /* * Enable and Lock the Advanced Encryption Standard (AES-NI) * feature register diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 22e8862..e1fc431 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -72,6 +72,7 @@ #define PRMRR_PHYS_MASK_LOCK (1 << 10) #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_POWER_CTL 0x1fc +#define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301