Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63090 )
Change subject: mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO ......................................................................
mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO
Currently, we control the GPP_D0 in the flash_fp_mcu in order to program the component's firmware. If we set this pin to NC, then we can't control the GPP_D0 output low/high and that make the system fails to program the component's firmware. This patch sets the GPP_D0 to GPO to fix it.
BUG=b:204679292 BRANCH=firmware-brya-14505.B TEST=program the component's firmware
Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Signed-off-by: Zhuohao Lee zhuohao@chromium.org --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63090/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index ed0416b..c540d76 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -118,7 +118,7 @@ PAD_NC(GPP_C7, NONE),
/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */