Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29166
Change subject: soc/amd/stoneyridge: Remove DEV_D18F4 definition ......................................................................
soc/amd/stoneyridge: Remove DEV_D18F4 definition
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is the same as SOC_PM_DEV. Remove the definition, and replace its use in tsc_freq.c with SOC_PM_DEV.
BUG=b:117754424 TEST=Build and boot grunt.
Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/tsc_freq.c 2 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29166/1
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 865cf71..5fddc52 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -145,12 +145,6 @@ #define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) -#if !defined(__SIMPLE_DEVICE__) - #include <device/device.h> - #define DEV_D18F4 dev_find_slot(0, PM_DEVFN) -#else - #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC) -#endif
/* Northbridge Configuration */ #define NB_DEV 0x18 diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 8c18884..a8ed7c6 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -36,7 +36,7 @@ * to the "Software P-state Numbering" section, P0 is the highest * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). */ - boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL) + boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
msr = rdmsr(PSTATE_0_MSR + boost_states);