Patch merged into coreboot/master: nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change

the following patch was just integrated into master:
commit 4488d7371a2b05e8f1f6952cc969821dfcd4ce42
Author: Timothy Pearson 
Date:   Fri Apr 22 22:16:45 2016 -0500

nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change

When more than one DIMM is installed on a DCT, only the first DIMM
    delay values are scaled to the new memory clock frequency after a
    memory clock change during write leveling.

Store the previous memory clock of each DIMM during write leveling
    to ensure that every DIMM has its delay values rescaled.

Change-Id: I56e816d3d3256925598219d92783246f5f4ab567
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/14479
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand 
    Reviewed-by: Martin Roth

See https://review.coreboot.org/14479 for details.

-gerrit