Change in coreboot[master]: [WIP] soc/intel/common: Add InSMM.STS support

[Michael Niewöhner (Code Review)]

Attention is currently required from: Nico Huber, Benjamin Doron, Paul Menzel, Angel Pons, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51796 )

Change subject: [WIP] soc/intel/common: Add InSMM.STS support
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Patch Set 6:

(2 comments)

File src/soc/intel/common/block/smm/smihandler.c:

https://review.coreboot.org/c/coreboot/+/51796/comment/98eb2b72_7cd398b4 
PS6, Line 276: 0x1fe
> Yeah, the thing is... […]

do we know which are supported and which not?

https://review.coreboot.org/c/coreboot/+/51796/comment/bd15e550_dd9af896 
PS6, Line 267: 	msr_t msr = {
             : 		.lo = read32((void *)(uintptr_t)0xfed30880),
             : 		.hi = 0,
             : 	};
             : 	if (enable_writes)
             : 		msr.lo |= 1;
             : 	else
             : 		msr.lo &= ~1;
             : 
             : 	wrmsr(0x1fe, msr);
             :
> This would read MSR 0x1fe, and I don't know what happens in that case. […]

ok, two questions:
1) what is that msr? haven't found it on a quick search
2) do we have to write the value from that mem address when enable_writes == 0?