HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44924 )
Change subject: nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a) ......................................................................
nb/intel/haswell/memmap.c: Use ALIGN_DOWN(x, a)
Also order and add missing includes.
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/memmap.c 1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44924/1
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb..2618754 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,11 +4,12 @@ #define __SIMPLE_DEVICE__
#include <arch/romstage.h> -#include <commonlib/helpers.h> +#include <cbmem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <types.h> + #include "haswell.h"
static uintptr_t smm_region_start(void) @@ -18,7 +19,7 @@ * 1 MiB alignment. */ uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return tom & ~((1 << 20) - 1); + return ALIGN_DOWN(tom, 1 * MiB); }
void *cbmem_top_chipset(void)
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44924
to look at the new patch set (#2).
Change subject: {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) ......................................................................
{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/memmap.c M src/soc/intel/broadwell/memmap.c 2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44924/2
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44924
to look at the new patch set (#3).
Change subject: {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) ......................................................................
{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/memmap.c M src/soc/intel/broadwell/memmap.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44924/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44924 )
Change subject: {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44924 )
Change subject: {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) ......................................................................
{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/haswell/memmap.c M src/soc/intel/broadwell/memmap.c 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb..807ee2a 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,7 +18,7 @@ * 1 MiB alignment. */ uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return tom & ~((1 << 20) - 1); + return ALIGN_DOWN(tom, 1 * MiB); }
void *cbmem_top_chipset(void) diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index bada5fd..4673cce 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -18,7 +18,7 @@ * must be calculated from the size in MiB in bits 11:4. */ uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); - uintptr_t tom = dpr & ~((1 << 20) - 1); + uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);
/* Subtract DMA Protected Range size if enabled */ if (dpr & DPR_EPM)
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)