Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Angel Pons, Kane Chen, Patrick Rudolph.
Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 17:

(3 comments)

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/60009/comment/a8785979_a0b5d5ba 
PS16, Line 411: 0xff: 648 MHz
> Looks like 0xff is the default setting (a value of 7 also specifies 648 MHz). […]

Done

https://review.coreboot.org/c/coreboot/+/60009/comment/efc02eeb_52c5d12b 
PS16, Line 408: /*
              : 	 * Core Display Clock Frequency selection
              : 	 * 0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz,
              : 	 * 6: 556.8 MHz, 7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz
              : 	 */
              : 	uint8_t CdClock;
> Why not use an enum? […]

Done

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/a4eda88a_c00b027c 
PS16, Line 212: params->CdClock = config->CdClock;
> To handle non-zero default values: […]

Done