Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57330 )
Change subject: mb/google/brya: Enable SaGv support for baseboard ......................................................................
mb/google/brya: Enable SaGv support for baseboard
This patch enabled the SaGv support for ADL-P brya baseboard.
TEST=Use RMT tool to verify the margins with FSP debug/RMT logs and also run "stressapptest" to check if any memory-related issue.
Signed-off-by: Marx Wang marx.wang@intel.com Change-Id: If109915f2cd3d8df2d74f84fb85e1812e63cc11c --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/57330/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 25b81eb..2d758d6 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,6 +1,7 @@ chip soc/intel/alderlake
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "SaGv" = "SaGv_Enabled"
# GPE configuration register "pmc_gpe0_dw0" = "GPP_A"