Change in coreboot[master]: soc/intel/common: Add option to disable eSPI SMI at runtime

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29535

Change subject: soc/intel/common: Add option to disable eSPI SMI at runtime
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soc/intel/common: Add option to disable eSPI SMI at runtime

Add an option that will disable eSPI SMI when ACPI mode is enabled,
and re-enable eSPI SMI when ACPI mode is disabled.  Additionally it
ensures eSPI SMI is disabled on the ACPI OS resume path.

This allows a mainboard to ensure that the Embedded Controller will
not be able to assert SMI at runtime when booted into an ACPI aware
operating system.

This was tested on a Sarien board with the Wilco EC to ensure that
the eSPI SMI enable bit is clear when booted into the OS, and remains
clear after resume.

Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c
Signed-off-by: Duncan Laurie 
---
M src/soc/intel/common/block/smm/Kconfig
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smm.c
3 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29535/1

diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 909382e..cc6bc44 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -8,6 +8,14 @@
    help
      Intel Processor trap flag if it is supported

+config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS
+	bool
+	default n
+	help
+	  Disable eSPI SMI when ACPI mode is enabled.  This will
+	  prevent the embedded controller from asserting SMI when
+	  booted into an ACPI aware OS.
+
 config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
    int
    default 100 if CHROMEOS
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 9e8d346..0832bb5 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -362,10 +362,14 @@
    	break;
    case APM_CNT_ACPI_DISABLE:
    	pmc_disable_pm1_control(SCI_EN);
+		if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
+			pmc_enable_smi(ESPI_SMI_EN);
    	printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
    	break;
    case APM_CNT_ACPI_ENABLE:
    	pmc_enable_pm1_control(SCI_EN);
+		if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
+			pmc_disable_smi(ESPI_SMI_EN);
    	printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
    	break;
    case APM_CNT_GNVS_UPDATE:
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index 6059995..d929975 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */

+#include <bootstate.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <intelblocks/pmclib.h>
@@ -93,3 +94,11 @@
    *start = (void *)sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }
+
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)
+static void smm_disable_espi(void *dest)
+{
+	pmc_disable_smi(ESPI_SMI_EN);
+}
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, smm_disable_espi, NULL);
+#endif