Change in coreboot[master]: [WIP]Allow to build romstage sources inside the bootblock

[Arthur Heymans (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Philipp Hug, Michał Żygowski, Martin Roth, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Ron Minnich, Piotr Król, Felix Held.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55068 )

Change subject: [WIP]Allow to build romstage sources inside the bootblock
......................................................................

[WIP]Allow to build romstage sources inside the bootblock

Having a separate romstage is only desirable:
 - with advanced setups like vboot or normal/fallback
 - boot medium is slow at startup (some ARM SOCs)
 - bootblock is limited in size (Intel APL 32K)

When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.

For now this feature is x86 only, but it would be easy to change that
for other arch.

TODO make this option only visible when it makes sense

TESTED: works on qemu x86

Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans 
---
M Makefile.inc
M src/Kconfig
M src/arch/x86/Makefile.inc
M src/drivers/amd/agesa/def_callouts.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/usb/ehci_debug.c
M src/include/cbmem.h
M src/lib/imd_cbmem.c
M src/lib/prog_loaders.c
M src/lib/program.ld
M src/lib/timestamp.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/lippert/frontrunner-af/sema.c
M src/mainboard/pcengines/apu1/BiosCallOuts.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/common/block/pi/def_callouts.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/cavium/cn81xx/sdram.c
M src/soc/intel/quark/storage_test.c
M src/soc/sifive/fu540/clock.c
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/i82801gx/early_init.c
M src/southbridge/intel/i82801ix/early_init.c
M src/southbridge/intel/i82801jx/early_init.c
M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
28 files changed, 53 insertions(+), 36 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/1

diff --git a/Makefile.inc b/Makefile.inc
index eb505e5..bfcc042 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1167,6 +1167,7 @@
    @printf "    CBFSPRINT  $(subst $(obj)/,,$(@))\n\n"
    $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions))

+ifeq ($(CONFIG_SEPARATE_ROMSTAGE),y)
 cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage
 $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf
 $(CONFIG_CBFS_PREFIX)/romstage-type := stage
@@ -1201,6 +1202,9 @@
 ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y)
 $(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB)
 endif
+else # CONFIG_SEPARATE_ROMSTAGE
+postinclude-hooks += $$(eval bootblock-srcs += $$(romstage-srcs))
+endif

cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
 $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
diff --git a/src/Kconfig b/src/Kconfig
index 6d0ba0f..cb0c18b 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -166,6 +166,10 @@
      user-selectable. (There's no real point in offering this to the user
      anyway... if it works and saves boot time, you would always want it.)

+config SEPARATE_ROMSTAGE
+	bool "Build a separate romstage"
+	default y
+
 config INCLUDE_CONFIG_FILE
    bool "Include the coreboot .config file into the ROM image"
    # Default value set at the end of the file
@@ -1317,6 +1321,7 @@

config HAVE_ROMSTAGE
    bool
+	depends on SEPARATE_ROMSTAGE
    default y

config HAVE_RAMSTAGE
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 957beed..1ee8b9f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -140,11 +140,11 @@

ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)

-romstage-y += assembly_entry.S
-romstage-y += romstage.c
+romstage-$(CONFIG_SEPARATE_ROMSTAGE) += assembly_entry.S
+romstage-$(CONFIG_SEPARATE_ROMSTAGE) += romstage.c
 romstage-y += boot.c
 romstage-y += post.c
-romstage-y += gdt_init.S
+romstage-$(CONFIG_SEPARATE_ROMSTAGE) += gdt_init.S
 romstage-y += cpu_common.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c
index 5f52ca0..8eb629c 100644
--- a/src/drivers/amd/agesa/def_callouts.c
+++ b/src/drivers/amd/agesa/def_callouts.c
@@ -129,7 +129,7 @@

AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	if (!ENV_ROMSTAGE)
+	if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	return AGESA_UNSUPPORTED;

return AmdMemoryReadSPD (Func, Data, ConfigPtr);
@@ -139,7 +139,7 @@
 {
    AGESA_READ_SPD_PARAMS *info = ConfigPtr;

-	if (!ENV_ROMSTAGE)
+	if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	return AGESA_UNSUPPORTED;

if (info->MemChannelId > 0)
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c
index 31db0b6..c89745c 100644
--- a/src/drivers/amd/agesa/state_machine.c
+++ b/src/drivers/amd/agesa/state_machine.c
@@ -18,7 +18,7 @@
 #include "Dispatcher.h"
 #endif

-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
 #include <PlatformMemoryConfiguration.h>
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
 #endif
@@ -262,7 +262,7 @@
    if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id)
    	timestamp_add_now(task.ts_entry_id);

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	final = romstage_dispatch(cb, func, StdHeader);

if (ENV_RAMSTAGE)
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
index fd8316e..9244f59 100644
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -110,7 +110,7 @@
 {
    uint32_t *list_loc;

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	return fsp_hob_list_ptr;
    list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME);
    return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL;
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index e9809e1..656ec81 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -78,7 +78,7 @@
    	return CB_ERR;
    }

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	soc_validate_fsp_version(hdr);

return CB_SUCCESS;
@@ -119,7 +119,7 @@

static inline bool fspm_env(void)
 {
-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	return true;
    return false;
 }
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 2fbdf3a..7631e8f 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -681,7 +681,7 @@
    struct ehci_debug_info *dbg_info_cbmem;
    int rv;

-	if (ENV_ROMSTAGE) {
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))) {
    	/* Move state from CAR to CBMEM. */
    	struct ehci_debug_info *dbg_info = dbgp_ehci_info();
    	dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG,
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index ec2b928..f817c3f 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -114,7 +114,7 @@
    section(".rodata.cbmem_init_hooks"))) = init_fn_;
 #define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \
    static cbmem_init_hook_t init_fn_ ## _unused_pc_ = init_fn_;
-#elif ENV_ROMSTAGE
+#elif ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
 #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \
    static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \
    section(".rodata.cbmem_init_hooks"))) = init_fn_;
@@ -157,7 +157,7 @@
  */
 static inline int cbmem_possibly_online(void)
 {
-	if (ENV_BOOTBLOCK)
+	if (ENV_BOOTBLOCK && CONFIG(SEPARATE_ROMSTAGE))
    	return 0;

if (ENV_SEPARATE_VERSTAGE && !CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index 4b7c412..66fa440 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -17,7 +17,7 @@

void *cbmem_top(void)
 {
-	if (ENV_ROMSTAGE) {
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))) {
    	static void *top;
    	if (top)
    		return top;
@@ -206,8 +206,9 @@
    imd_region_used(&imd, baseptr, size);
 }

-#if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) \
-	&& (ENV_POSTCAR || ENV_ROMSTAGE))
+#if ENV_PAYLOAD_LOADER							\
+	|| (CONFIG(EARLY_CBMEM_LIST)					\
+	    && (ENV_POSTCAR || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))))
 /*
  * -fdata-sections doesn't work so well on read only strings. They all
  * get put in the same section even though those strings may never be
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 40f51eb..19df3c1 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include "commonlib/timestamp_serialized.h"
 #include <stdlib.h>
 #include <cbfs.h>
 #include <cbmem.h>
@@ -15,9 +16,15 @@
 #include <symbols.h>
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
+#include <romstage_common.h>

void run_romstage(void)
 {
+	if (!CONFIG(SEPARATE_ROMSTAGE)) {
+		timestamp_add_now(TS_START_ROMSTAGE);
+		romstage_main();
+	}
+
    struct prog romstage =
    	PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage");

@@ -84,7 +91,7 @@
    	timestamp_add_now(TS_END_POSTCAR);

/* Call "end of romstage" here if postcar stage doesn't exist */
-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	timestamp_add_now(TS_END_ROMSTAGE);

/*
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 1c5cda4..4d8e7e3 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -24,7 +24,7 @@
    *(.text);
    *(.text.*);

-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_POSTCAR
+#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_POSTCAR || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
    . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
    _cbmem_init_hooks = .;
    KEEP(*(.rodata.cbmem_init_hooks_early));
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 7347d07..ed30fbb 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -215,7 +215,7 @@

/* First time into romstage we make a clean new table. For platforms that travel
       through this path on resume, ARCH_X86 S3, timestamps are also reset. */
-	if (ENV_ROMSTAGE) {
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))) {
    	ts_cbmem_table = timestamp_alloc_cbmem_table();
    } else {
    	/* Find existing table in cbmem. */
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index 518bc95..4ee7768 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -180,7 +180,7 @@
    AGESA_READ_SPD_PARAMS *info = ConfigPtr;
    u8 index;

-	if (!ENV_ROMSTAGE)
+	if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))))
    	return AGESA_UNSUPPORTED;

if (CONFIG(BAP_E20_DDR3_1066))
diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c
index e80cc12..465f7ad 100644
--- a/src/mainboard/lippert/frontrunner-af/sema.c
+++ b/src/mainboard/lippert/frontrunner-af/sema.c
@@ -53,7 +53,7 @@
    char one_spd_byte;

/* Fake read just to setup SMBUS controller. */
-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	smbus_readSpd(0xa0, &one_spd_byte, 1);

/* Notify the SMC we're alive and kicking, or after a while it will
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c
index 4944a85..2267434 100644
--- a/src/mainboard/pcengines/apu1/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c
@@ -38,7 +38,7 @@
 {
    AGESA_READ_SPD_PARAMS *info = ConfigPtr;

-	if (!ENV_ROMSTAGE)
+	if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))))
    	return AGESA_UNSUPPORTED;

u8 index = get_spd_offset();
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index d17dc366..49cbd76 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -107,7 +107,7 @@
 {
    AGESA_READ_SPD_PARAMS	*info = ConfigPtr;

-	if (!ENV_ROMSTAGE)
+	if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	return AGESA_UNSUPPORTED;

u8 index = get_spd_offset();
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index ff52fbd..05c39c6 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -67,7 +67,7 @@
    	aip->NewStructPtr = buf;
    	aip->NewStructSize = len;
    } else {
-		if (ENV_ROMSTAGE)
+		if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    		aip->AllocationMethod = PreMemHeap;
    	if (ENV_RAMSTAGE)
    		aip->AllocationMethod = PostMemDram;
@@ -412,7 +412,7 @@
    StdHeader = aip->NewStructPtr;
    StdHeader->Func = func;

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	status = romstage_dispatch(StdHeader);
    if (ENV_RAMSTAGE)
    	status = ramstage_dispatch(StdHeader);
diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c
index 2ee7f46..5e6a2d8 100644
--- a/src/soc/amd/common/block/pi/def_callouts.c
+++ b/src/soc/amd/common/block/pi/def_callouts.c
@@ -22,7 +22,7 @@
 #else
 const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
    /* Required callouts */
-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
    { AGESA_HALT_THIS_AP,             agesa_HaltThisAp },
 #endif
    { AGESA_ALLOCATE_BUFFER,          agesa_AllocateBuffer },
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index ba0f0ee..8f335bb 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -86,7 +86,7 @@
    DEVTREE_CONST struct soc_amd_stoneyridge_config *conf;
    AGESA_READ_SPD_PARAMS *info = ConfigPtr;

-	if (!ENV_ROMSTAGE)
+	if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	return AGESA_UNSUPPORTED;

dev = pcidev_path_on_root(DCT_DEVFN);
diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c
index 080adc0..d82e818 100644
--- a/src/soc/cavium/cn81xx/sdram.c
+++ b/src/soc/cavium/cn81xx/sdram.c
@@ -29,7 +29,7 @@
 #define BDK_RNM_CTL_STATUS	0
 #define BDK_RNM_RANDOM		0x100000

-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
 /* Enable RNG for DRAM init */
 static void rnm_init(void)
 {
diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c
index 1eed84e..47b8e84 100644
--- a/src/soc/intel/quark/storage_test.c
+++ b/src/soc/intel/quark/storage_test.c
@@ -159,7 +159,7 @@

/* Get the structure addresses */
    media = NULL;
-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	media = (struct storage_media *)drivers_storage;
    else
    	media = cbmem_find(CBMEM_ID_STORAGE_DATA);
@@ -227,7 +227,7 @@
 }
 #endif

-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
 static void copy_storage_structures(int is_recovery)
 {
    struct storage_media *media;
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index 977f938..a01e933 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -56,7 +56,7 @@
 #define PRCI_DEVICESRESET_GEMGXL_RST_N(x)   (((x) & 0x1)  << 5)

/* Clock initialization should only be done in romstage. */
-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
 struct pll_settings {
    unsigned int divr:6;
    unsigned int divf:9;
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 6ed3dce..5d27aef 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -310,6 +310,6 @@

setup_pch_gpios(&mainboard_gpio_map);

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	enable_smbus();
 }
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index c8a6117..0cb803b 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -58,7 +58,7 @@

#define TCO_BASE 0x60

-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))
 void i82801gx_early_init(void)
 {
    enable_smbus();
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index f781098..214b588 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -47,7 +47,7 @@
 {
    const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	enable_smbus();

/* Set up RCBA. */
diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c
index 327c8fc..5633226 100644
--- a/src/southbridge/intel/i82801jx/early_init.c
+++ b/src/southbridge/intel/i82801jx/early_init.c
@@ -69,7 +69,7 @@
 {
    const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);

-	if (ENV_ROMSTAGE)
+	if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
    	enable_smbus();

printk(BIOS_DEBUG, "Setting up static southbridge registers...");
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
index b1a346a..f68fb2b 100644
--- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -2,7 +2,7 @@
 #define AGESA_ENTRY_CFG_H

-#if ENV_ROMSTAGE
+#if ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE))

#define AGESA_ENTRY_INIT_RESET		TRUE
 #define AGESA_ENTRY_INIT_EARLY		TRUE