Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters

[Jonathan Zhang (Code Review)]

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Jingle Hsu, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40385

to look at the new patch set (#21).

Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
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soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters

Configure FSP-M UPD parameters.

These parameters are proved to work on OCP DeltaLake server.
Discussion is on-going with Intel FSP engineering team on what
those parameters mean, and why those value settings are necessary.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67
---
M src/soc/intel/xeon_sp/cpx/romstage.c
1 file changed, 45 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/40385/21