Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
drivers/intel/usb4: Add driver for USB4 PCIe root port
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Signed-off-by: Duncan Laurie dlaurie@google.com Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb --- A src/drivers/intel/usb4/Kconfig A src/drivers/intel/usb4/Makefile.inc A src/drivers/intel/usb4/pcie/Kconfig A src/drivers/intel/usb4/pcie/Makefile.inc A src/drivers/intel/usb4/pcie/chip.h A src/drivers/intel/usb4/pcie/pcie.c 6 files changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/1
diff --git a/src/drivers/intel/usb4/Kconfig b/src/drivers/intel/usb4/Kconfig new file mode 100644 index 0000000..93501aa --- /dev/null +++ b/src/drivers/intel/usb4/Kconfig @@ -0,0 +1 @@ +source "src/drivers/intel/usb4/*/Kconfig" diff --git a/src/drivers/intel/usb4/Makefile.inc b/src/drivers/intel/usb4/Makefile.inc new file mode 100644 index 0000000..4c02663 --- /dev/null +++ b/src/drivers/intel/usb4/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += ./* diff --git a/src/drivers/intel/usb4/pcie/Kconfig b/src/drivers/intel/usb4/pcie/Kconfig new file mode 100644 index 0000000..6363939 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_INTEL_USB4_PCIE + bool diff --git a/src/drivers/intel/usb4/pcie/Makefile.inc b/src/drivers/intel/usb4/pcie/Makefile.inc new file mode 100644 index 0000000..b5d3e94 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_PCIE) += pcie.c diff --git a/src/drivers/intel/usb4/pcie/chip.h b/src/drivers/intel/usb4/pcie/chip.h new file mode 100644 index 0000000..b821d47 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_PCIE_H__ +#define __DRIVERS_INTEL_USB4_PCIE_H__ + +struct drivers_intel_usb4_pcie_config { + const char *desc; + + /* USB port number */ + unsigned int port_id; + + /* Pointer to USB4 device that this PCIe root port is routed to. */ + DEVTREE_CONST struct device *usb4_port; +}; + +#endif /* __DRIVERS_INTEL_USB4_PCIE_H__ */ diff --git a/src/drivers/intel/usb4/pcie/pcie.c b/src/drivers/intel/usb4/pcie/pcie.c new file mode 100644 index 0000000..bba803f --- /dev/null +++ b/src/drivers/intel/usb4/pcie/pcie.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci_def.h> +#include <stdlib.h> +#include <string.h> +#include "chip.h" + +#define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" +#define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" + +static void usb4_pcie_fill_ssdt(const struct device *dev) +{ + struct drivers_intel_usb4_pcie_config *config = dev->chip_info; + struct acpi_dp *dsd, *pkg; + const char *usb4_path; + + if (!dev->enabled) + return; + if (!config->usb4_port) + return; + + /* Get ACPI path to USB4 device. */ + usb4_path = acpi_device_path(config->usb4_port); + if (!usb4_path) + return; + usb4_path = strdup(usb4_path); + + acpigen_write_scope(acpi_device_path(dev)); + + /* Add pointer to USB4 port controller. */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_reference(dsd, "usb4-host-interface", usb4_path); + acpi_dp_add_integer(dsd, "usb4-port-number", config->port_id); + + /* Indicate that device supports hotplug in D3. */ + pkg = acpi_dp_new_table(PCI_HOTPLUG_IN_D3_UUID); + acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that port is external. */ + pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); + acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); + acpi_dp_add_integer(pkg, "UID", config->port_id); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); +} + +static struct device_operations usb4_pcie_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_pcie_fill_ssdt, +}; + +static void usb4_pcie_enable(struct device *dev) +{ + struct drivers_intel_usb4_pcie_config *config = dev->chip_info; + + dev->ops = &usb4_pcie_dev_ops; + + if (config->desc) + dev->name = config->desc; + else + config->desc = dev->chip_ops->name; +} + +struct chip_operations drivers_intel_usb4_pcie_ops = { + CHIP_NAME("Intel USB4 PCIe Root Port") + .enable_dev = usb4_pcie_enable +};
Tim Wawrzynczak has uploaded a new patch set (#2) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
drivers/intel/usb4: Add driver for USB4 PCIe root port
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com --- A src/drivers/intel/usb4/Kconfig A src/drivers/intel/usb4/Makefile.inc A src/drivers/intel/usb4/pcie/Kconfig A src/drivers/intel/usb4/pcie/Makefile.inc A src/drivers/intel/usb4/pcie/chip.h A src/drivers/intel/usb4/pcie/pcie.c 6 files changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/Kconfig:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 2: bool depends on HAVE_ACPI_TABLES?
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/chip.h:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 9: USB port number Is this the port number as assigned in hardware? Or is this just a unique number assigned for each port under a particular controller?
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 17: dev->chip_info; config_of(dev)
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 17: struct const
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 23: if (!config->usb4_port) Should there be an error printed in case usb4_port device is not found?
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 29: return; Print error in this case?
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/chip.h:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 9: USB port number
Is this the port number as assigned in hardware? Or is this just a unique number assigned for each p […]
as far as I can tell this is defined in the soc at a platform level but not in any place that I've seen that we can read it from. this was in the static asl before and this driver tries to move it to the chipset.cb.
maybe a comment would be useful to indicate it is expected to be set by the soc and not the mainboard.
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 23: if (!config->usb4_port)
Should there be an error printed in case usb4_port device is not found?
I didn't initially because these should be set at the soc level and not be an issue at the mainboard, but it doesn't hurt to have more output for the next soc implementation that forgets.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/chip.h:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 9: USB port number
as far as I can tell this is defined in the soc at a platform level but not in any place that I've s […]
We don't have a really great name for this identifier 😞 I'll add a comment.
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 17: struct
const
Done
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 17: dev->chip_info;
config_of(dev)
Done
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 23: if (!config->usb4_port)
I didn't initially because these should be set at the soc level and not be an issue at the mainboard […]
Done
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 29: return;
Print error in this case?
Done
Tim Wawrzynczak has uploaded a new patch set (#3) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ......................................................................
drivers/intel/usb4: Add driver for USB4 PCIe root port
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com --- A src/drivers/intel/usb4/Kconfig A src/drivers/intel/usb4/Makefile.inc A src/drivers/intel/usb4/pcie/Kconfig A src/drivers/intel/usb4/pcie/Makefile.inc A src/drivers/intel/usb4/pcie/chip.h A src/drivers/intel/usb4/pcie/pcie.c 6 files changed, 107 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/3
Tim Wawrzynczak has uploaded a new patch set (#4) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c 4 files changed, 123 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/4
Tim Wawrzynczak has uploaded a new patch set (#8) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c 4 files changed, 123 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/8
Tim Wawrzynczak has uploaded a new patch set (#9) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c 3 files changed, 112 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/9
Tim Wawrzynczak has uploaded a new patch set (#11) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/chipset.cb 7 files changed, 138 insertions(+), 110 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/11
Tim Wawrzynczak has uploaded a new patch set (#12) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c 4 files changed, 119 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/12
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... File src/drivers/intel/usb4/pcie/Kconfig:
https://review.coreboot.org/c/coreboot/+/44915/2/src/drivers/intel/usb4/pcie... PS2, Line 2: bool
depends on HAVE_ACPI_TABLES?
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 12: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/Kconfig:
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... PS12, Line 12: HAVE_ACPI_TABLES Not required since the driver is doing more than just handling ACPI tables?
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... PS12, Line 51: port_id = PCI_FUNC(dev->path.pci.devfn); I am still not completely sure about this. I don't think we should represent the dummy/virtual device created under the RP as PCI device. Posted a comment on next CL in this series as well.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... PS12, Line 83: scan_generic_bus Should this be scan_static_bus since that will allow walking downstream from the child in case it is a bridge.
Tim Wawrzynczak has uploaded a new patch set (#13) to the change originally created by Duncan Laurie. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c 4 files changed, 118 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/13
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 13: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/Kconfig:
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... PS12, Line 12: HAVE_ACPI_TABLES
Not required since the driver is doing more than just handling ACPI tables?
Oops yep forget to remove it here when I added the #if CONFIGs below.
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/12/src/soc/intel/common/block... PS12, Line 83: scan_generic_bus
Should this be scan_static_bus since that will allow walking downstream from the child in case it is […]
Done
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/chip.h A src/soc/intel/common/block/usb4/pcie.c 4 files changed, 118 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index 1516e75..be0b378 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -4,3 +4,10 @@ help Minimal PCI Driver for enabling SSDT generation for the DMA component of Intel Thunderbolt/USB4 ports. + +config SOC_INTEL_COMMON_BLOCK_USB4_PCIE + bool + default n + help + Chip driver for adding PCI ops and SSDT generation for common Intel + USB4/Thunderbolt root ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc index 7dad4ba..89ce426 100644 --- a/src/soc/intel/common/block/usb4/Makefile.inc +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4_PCIE) += pcie.c diff --git a/src/soc/intel/common/block/usb4/chip.h b/src/soc/intel/common/block/usb4/chip.h new file mode 100644 index 0000000..f2eee4d --- /dev/null +++ b/src/soc/intel/common/block/usb4/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_PCIE_H__ +#define __DRIVERS_INTEL_USB4_PCIE_H__ + +struct soc_intel_common_block_usb4_config { + const char *desc; + + /* Pointer to USB4 device that this PCIe root port is routed to. */ + DEVTREE_CONST struct device *usb4_port; +}; + +#endif /* __DRIVERS_INTEL_USB4_PCIE_H__ */ diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c new file mode 100644 index 0000000..e37d5f4 --- /dev/null +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <types.h> +#include "chip.h" + +#define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" +#define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" + +#if CONFIG(HAVE_ACPI_TABLES) +static void usb4_pcie_fill_ssdt(const struct device *dev) +{ + const struct soc_intel_common_block_usb4_config *config; + const struct device *parent; + struct acpi_dp *dsd, *pkg; + const char *usb4_path; + int port_id; + + /* Get parent PCI device */ + parent = dev->bus->dev; + if (!parent) { + printk(BIOS_ERR, "%s: Unable to find parent device\n", __func__); + return; + } + + if (!dev->enabled || !parent->enabled) + return; + + config = config_of(dev); + if (!config->usb4_port) { + printk(BIOS_ERR, "%s: Unable to find reference to usb4_port\n", __func__); + return; + } + + /* Get ACPI path to USB4 device. */ + usb4_path = acpi_device_path(config->usb4_port); + if (!usb4_path) { + printk(BIOS_ERR, "%s: Unable to find ACPI path for usb4_port\n", __func__); + return; + } + + usb4_path = strdup(usb4_path); + port_id = dev->path.generic.id; + + acpigen_write_scope(acpi_device_path(dev)); + + /* Add pointer to USB4 port controller. */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_reference(dsd, "usb4-host-interface", usb4_path); + acpi_dp_add_integer(dsd, "usb4-port-number", port_id); + + /* Indicate that device supports hotplug in D3. */ + pkg = acpi_dp_new_table(PCI_HOTPLUG_IN_D3_UUID); + acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that port is external. */ + pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); + acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); + acpi_dp_add_integer(pkg, "UID", port_id); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); +} +#endif + +static struct device_operations usb4_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_static_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = usb4_pcie_fill_ssdt, +#endif +}; + +static void pcie_enable(struct device *dev) +{ + dev->ops = &usb4_dev_ops; +} + +struct chip_operations soc_intel_common_block_usb4_ops = { + CHIP_NAME("Intel USB4 Root Port") + .enable_dev = pcie_enable +};
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... PS14, Line 80: .read_resources = pci_dev_read_resources, : .set_resources = pci_dev_set_resources, : .enable_resources = pci_dev_enable_resources, This is actually not correct any more. Since the driver switched from handling a PCI device to a generic device, this is setting the operations incorrectly.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... PS14, Line 53: dev This too. This will have to be parent.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44915 )
Change subject: soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports ......................................................................
Patch Set 14:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... File src/soc/intel/common/block/usb4/pcie.c:
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... PS14, Line 53: dev
This too. This will have to be parent.
Yeah, sorry about that 😞
https://review.coreboot.org/c/coreboot/+/44915/14/src/soc/intel/common/block... PS14, Line 80: .read_resources = pci_dev_read_resources, : .set_resources = pci_dev_set_resources, : .enable_resources = pci_dev_enable_resources,
This is actually not correct any more. […]
Yep, needs to go to the parent.
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Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
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Nick Vaccaro (Code Review)
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Tim Wawrzynczak (Code Review)