Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 )

Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
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Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG@15 
PS15, Line 15: implementation for three platforms.
> I'm not sure that's true across the board. […]

Well I know for AGESA/PI rdtscll() rescales during raminit. That's why they are not at TSC_MONOTONIC_TIMER yet. For the duration of coreboot execution, do we need to care about C/P-states or other clock throttling?

Then again, I belive LAPIC_MONOTONIC_TIMER did not work either for AMD. Marshall, Martin; do you reemember something about this on amd/stoneyridge? Like udelay() failing with UART8250MEM.