Change in coreboot[master]: soc/intel/apl/graphics: add missing left-shift

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48759 )

Change subject: soc/intel/apl/graphics: add missing left-shift
......................................................................

soc/intel/apl/graphics: add missing left-shift

According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.

Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/apollolake/graphics.c
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 24d4772..be13b5b 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -17,7 +17,8 @@
    const unsigned int offset = panel_idx * 0x100;
    uint32_t reg32;

-	reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET;
+	reg32 = (DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) << 4 & 0x1f0;
+	reg32 |= PANEL_POWER_RESET;
    write32(mmio + PCH_PP_CONTROL + offset, reg32);

reg32 = pp->up_delay_ms * 10 << 16;