Change in coreboot[master]: soc/intel/common/smbus: Don't clear random bits

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21072

Change subject: soc/intel/common/smbus: Don't clear random bits
......................................................................

soc/intel/common/smbus: Don't clear random bits

FSP might have done some settings for us there. Use pci_update_config32()
since the register is documented to be 32 bits wide.

Change-Id: I995e8a731a6958f10600174d031bb94f5a0a66db
Signed-off-by: Nico Huber 
---
M src/soc/intel/common/block/smbus/smbus.c
1 file changed, 2 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21072/1

diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 8ee38ee..e526baf 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -53,12 +53,10 @@
 static void pch_smbus_init(device_t dev)
 {
    struct resource *res;
-	u16 reg16;

/* Enable clock gating */
-	reg16 = pci_read_config32(dev, 0x80);
-	reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
-	pci_write_config32(dev, 0x80, reg16);
+	pci_update_config32(dev, 0x80,
+		~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)), 0);

/* Set Receive Slave Address */
    res = find_resource(dev, PCI_BASE_ADDRESS_4);